公开(公告)号：DE3279782D1

公开(公告)日：1989-07-27

申请号：DE3279782

申请日：1982-03-24

Applicant: IBM ,  IBM FRANCE

Inventor： GRANDGUILLOT MICHEL ,  MOLLIER PIERRE ,  NUEZ JEAN-PAUL

IPC: G11C11/413 ,  G11C8/06 ,  H03K5/151 ,  H03K5/15 ,  G11C8/00

Abstract: A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value ( phi ), the second one providing the complement ( phi ) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of ( phi ) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output phi . Transistor T11-2 in the second circuit prevents phi from going high as long as it is maintained on by the level provided by R10-1, R11-2 from phi .

公开(公告)号：FR2464598A1

公开(公告)日：1981-03-06

申请号：FR7922137

申请日：1979-08-28

Applicant: IBM FRANCE

Inventor： GRANDGUILLOT MICHEL ,  MOLLIER PIERRE ,  NUEZ JEAN-PAUL

IPC: H03K19/20 ,  H03K5/151 ,  H03K19/018 ,  H03K5/15 ,  G06F1/04