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    DECODING AND SELECTION CIRCUIT FOR MONOLITHIC MEMORY
    1.
    发明专利
    DECODING AND SELECTION CIRCUIT FOR MONOLITHIC MEMORY 未知

    公开(公告)号：DE3070584D1

    公开(公告)日：1985-06-05

    申请号：DE3070584

    申请日：1980-09-26

    Applicant: IBM ,  IBM FRANCE

    Inventor： BOUDON GERARD ,  DENIS BERNARD ,  DE GRIVEL VIRGINIE ,  MOLLIER PIERRE

    IPC: G11C11/41 ,  G11C11/413 ,  G11C11/415 ,  G11C16/08 ,  G11C17/18 ,  G11C11/40 ,  G11C11/24 ,  G11C17/00

    Abstract: A word line selection circuit includes a conventional Schottky diode decoder and a driver transistor which is connected to a word line. A word line is selected when the transistor is conductive and all associated diodes of the decoder are off. The base current of the driver transistor is defined by a control transistor whose conductivity is opposite to that of the driver transistor and which applies the selection current to the base of the driver transistor. A regulating transistor forms a current mirror with the control transistor to regulate the selection current. A compensation circuit associated with the regulating transistor modulates the collector current of the regulating transistor as a function of the driver transistor factor.

    TRUE/COMPLEMENT GENERATOR
    3.
    发明专利
    TRUE/COMPLEMENT GENERATOR 未知

    公开(公告)号：DE3279782D1

    公开(公告)日：1989-07-27

    申请号：DE3279782

    申请日：1982-03-24

    Applicant: IBM ,  IBM FRANCE

    Inventor： GRANDGUILLOT MICHEL ,  MOLLIER PIERRE ,  NUEZ JEAN-PAUL

    IPC: G11C11/413 ,  G11C8/06 ,  H03K5/151 ,  H03K5/15 ,  G11C8/00

    Abstract: A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value ( phi ), the second one providing the complement ( phi ) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of ( phi ) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output phi . Transistor T11-2 in the second circuit prevents phi from going high as long as it is maintained on by the level provided by R10-1, R11-2 from phi .

    8.
    发明专利
    未知

    公开(公告)号：DE3688139D1

    公开(公告)日：1993-04-29

    申请号：DE3688139

    申请日：1986-12-30

    Applicant: IBM

    Inventor： BAUGE MICHEL ,  MOLLIER PIERRE ,  YAMOUR YIANNIS JOHN ,  BOUDON GERARD ,  PETER JEAN-LUC

    IPC: G06F11/18 ,  G06F11/16 ,  G06F13/40

    Abstract: The duplicated circuit arrangement has at least two devices provided with drivers connected between the outputs of a processor and the lines of the device bus. The driving effort on the p bit mash data bus is shared so that each device transmits only a part of the p bit word. The transmitted part of the p bit word consists of a set of bits corresp. to the content of a determined section of the processor. The whole p bit word is available in integrality on the p bit mash data bus, where the sets of bits supplied by the two devices are reassembled.

    9.
    发明专利
    未知

    公开(公告)号：DE3788132D1

    公开(公告)日：1993-12-16

    申请号：DE3788132

    申请日：1987-12-01

    Applicant: IBM

    Inventor： BOUDON GERARD ,  ONG IENG ,  MOLLIER PIERRE

    IPC: H03K19/08 ,  H03K19/013 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/094

    Abstract: A multi base 2 input Bi-CMOS NAND circuit (30) is provided wherein an output node OUT connected to an output terminal (33) is coupled between pull up (31) and pull down (32) blocks. According to the present invention, the pull up block (31) is comprised of 2 identical basic cells, each comprised of a CMOS inverter (C31, C32) driving a NPN pull up transistor (T31, T32) mounted as an emitter follower. Logic signals (A31, A32) are applied on the inputs of the inverters (C31, C32), and the inverted signal (A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All emitters are tied altogether to perform an OR function and are connected to said output terminal (33). As standard, the pull down block (32) includes a logic stack (34) is comprised of 2 FETS (F31, F32) serially connected between said output node OUT and a discharge device such as a feedback NFET (Z), the gate of which is connected to said output node OUT. These 2 FETS are driving a NPN pull down transistor (T), the collector of which is also connected to the output node OUT.

    10.
    发明专利
    未知

    公开(公告)号：DE68924426T2

    公开(公告)日：1996-05-02

    申请号：DE68924426

    申请日：1989-10-26

    Applicant: IBM

    Inventor： MOLLIER PIERRE ,  NUEZ JEAN-PAUL ,  TANNHOF PASCAL

    IPC: H03K19/013 ,  H03K19/086

    Abstract: The base circuit (30) comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages (VEE1, VC) and a push-pull output buffer stage (32) connected between second and third supply voltages (VC, VEE2). The push-pull output buffer stage (32) comprises a pull-up transistor (TUP) and a pull-down transistor (TDN) connected in series with the circuit output node (OUT3) coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by said preamplifier. Both branches of the preamplifier are tied at a first output node (M). A current source (I) is connected to said first output node. The first branch comprises a logic block (LB) performing the desired logic function of the base circuit that is connected through a load resistor (R1) to said second supply voltage (VC). In this instance, logic block consists of three parallel-connected input NPN transistors (T1, T2, T3), whose emitters are coupled together at said first output node (M) for NOR operation. The second branch is comprised of a biasing/coupling block (BB) connected to said second supply voltage and coupled both to said first output node (M) and to base node (B) of said pull-down transistor. In a preferred embodiment, this block consists of a diode-connected transistor (TC) and of a resistor (RC) connected in series with the base node (B) coupled therebetween. This block ensures both the appropriate polarization of said nodes (M, B) in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal (S) from node M to node B in AC, when input transistors of the logic block (LB) are ON. Optionally, the AC transmission can be improved by mounting a capacitor (C) between said first output and base nodes. An antisaturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.

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