公开(公告)号：DE3070584D1

公开(公告)日：1985-06-05

申请号：DE3070584

申请日：1980-09-26

Applicant: IBM ,  IBM FRANCE

Inventor： BOUDON GERARD ,  DENIS BERNARD ,  DE GRIVEL VIRGINIE ,  MOLLIER PIERRE

IPC: G11C11/41 ,  G11C11/413 ,  G11C11/415 ,  G11C16/08 ,  G11C17/18 ,  G11C11/40 ,  G11C11/24 ,  G11C17/00

Abstract: A word line selection circuit includes a conventional Schottky diode decoder and a driver transistor which is connected to a word line. A word line is selected when the transistor is conductive and all associated diodes of the decoder are off. The base current of the driver transistor is defined by a control transistor whose conductivity is opposite to that of the driver transistor and which applies the selection current to the base of the driver transistor. A regulating transistor forms a current mirror with the control transistor to regulate the selection current. A compensation circuit associated with the regulating transistor modulates the collector current of the regulating transistor as a function of the driver transistor factor.

公开(公告)号：DE3374638D1

公开(公告)日：1987-12-23

申请号：DE3374638

申请日：1983-06-30

Applicant: IBM ,  IBM FRANCE

Inventor： BRUNIN ARMAND ,  DENIS BERNARD ,  BOUDON GERARD ,  MOLLIER PIERRE ,  STOPPA PHILIPPE

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/06 ,  H03K19/003 ,  H03K19/082 ,  H03K19/084 ,  H03K19/088

Abstract: Logic inputs are applied to the cathodes of Schottky diodes (D1-Dn) whose anodes are connected together to the base of a n-p-n input transistor (T1). A supplementary input (X) from a logic circuit (1) is applied to the emitter of the transistor (T1) whose collector drives the base of an inverting n-p-n output transistir (T2). Both transistors (T1,T2) have collector-to-base antisaturation Schottky diodes (S1,S2) with higher barrier values. Prediffused diodes, transistors and resistors can be wired at the first level of metallisation to constitute the desired logic circuits. Cells can be interconnected in dense arrays at the second and third levels.

公开(公告)号：FR2464598A1

公开(公告)日：1981-03-06

申请号：FR7922137

申请日：1979-08-28

Applicant: IBM FRANCE

Inventor： GRANDGUILLOT MICHEL ,  MOLLIER PIERRE ,  NUEZ JEAN-PAUL

IPC: H03K19/20 ,  H03K5/151 ,  H03K19/018 ,  H03K5/15 ,  G06F1/04

公开(公告)号：DE3279782D1

公开(公告)日：1989-07-27

申请号：DE3279782

申请日：1982-03-24

Applicant: IBM ,  IBM FRANCE

Inventor： GRANDGUILLOT MICHEL ,  MOLLIER PIERRE ,  NUEZ JEAN-PAUL

IPC: G11C11/413 ,  G11C8/06 ,  H03K5/151 ,  H03K5/15 ,  G11C8/00

Abstract: A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value ( phi ), the second one providing the complement ( phi ) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of ( phi ) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output phi . Transistor T11-2 in the second circuit prevents phi from going high as long as it is maintained on by the level provided by R10-1, R11-2 from phi .

公开(公告)号：DE3276516D1

公开(公告)日：1987-07-09

申请号：DE3276516

申请日：1982-12-28

Applicant: IBM ,  IBM FRANCE

Inventor： BOUDON GERARD ,  MOLLIER PIERRE ,  LEBESNERAIS GERARD

IPC: H04L25/38 ,  H04L25/45 ,  H04L25/48 ,  H04L25/49