公开(公告)号：EP4181179A1

公开(公告)日：2023-05-17

申请号：EP21208577.3

申请日：2021-11-16

Applicant: Imec VZW

Inventor： Karve, Gauri ,  Li, Yunlong ,  Haspeslagh, Luc ,  Soussan, Philippe ,  Sabuncuoglu Tezcan, Deniz

IPC: H01L21/683 ,  H01L27/146

Abstract: According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer (4) and one or more tiles (6) that are removably attached to said temporary wafer, preferably through a temporary adhesive layer (5). The tiles comprise a carrier portion (6a) and an active material portion (6b). The active material portion (6b) is attached to the temporary carrier (4). The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles (6). Then the back side of the carrier portions (6a) of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer (17), after which the temporary carrier wafer (4) is removed. The method results in a hybrid wafer comprising a planar top layer formed of the material of the continuous layer (1,22) with one or more islands embedded therein, the top layer of said islands being formed by the top layer of the active material portion (6b) of the one or more tiles (6).

公开(公告)号：EP2327658B1

公开(公告)日：2018-07-04

申请号：EP09177497.6

申请日：2009-11-30

Applicant: IMEC VZW

Inventor： Witvrouw, Ann ,  Haspeslagh, Luc ,  Claes, Gert

IPC: B81C1/00

CPC classification number: B81C1/00293 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2207/015 ,  B81C2203/0136 ,  B81C2203/0145 ,  B81C2203/0735 ,  B81C2203/0771

Abstract: A method is disclosed for manufacturing a sealed cavity comprised in a microelectronic device, comprising forming a sacrificial layer at least at locations where the cavity is to be provided, depositing a membrane layer on top of the sacrificial layer, patterning the membrane layer in at least two separate membrane layer blocks, removing the sacrificial laye through the membrane layer, and sealing the cavity by sealing the membrane layer, wherein patterning the membrane layer is performed after removal of the sacrificial layer; and associated microelectronic devices.

公开(公告)号：EP2327659B1

公开(公告)日：2018-07-11

申请号：EP09177498.4

申请日：2009-11-30

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven K.U. Leuven R&D

Inventor： Witvrouw, Ann ,  Haspeslagh, Luc ,  Guo, Bin

IPC: B81C1/00

CPC classification number: B81C1/00333 ,  B81B2201/0257 ,  B81B2201/0264

Abstract: A method is disclosed for manufacturing a semiconductor device, the method comprising - providing a substrate comprising a main surface with a non flat topography, the surface comprising substantial topography variations; - forming a first capping layer over the main surface; wherein, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluida to pass through. Associated membrane layers, capping layers and microelectronic devices have also been disclosed.

公开(公告)号：EP2407418A3

公开(公告)日：2014-04-09

申请号：EP11005669.4

申请日：2011-07-12

Applicant: IMEC vzw

Inventor： Guo, Bin ,  Haspeslagh, Luc

IPC: B81C1/00

CPC classification number: B81C1/00277 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/095

Abstract: A MEMS device 1 is disclosed comprising a cavity 5 containing a MEMS component 6, the cavity 5 being formed in a dielectric layer stack 3 having a thickness t d , whereby the cavity 5 and the dielectric layer stack 3 are sandwiched between a substrate 2 and a sealing dielectric layer 4 having a thickness t s , and whereby the MEMS component 6 is enclosed by at least one trench 8 extending over the thickness t d of the dielectric layer stack 3 and of the sealing dielectric t s .

公开(公告)号：EP2407418A2

公开(公告)日：2012-01-18

申请号：EP11005669.4

申请日：2011-07-12

Applicant: Imec VZW

Inventor： Guo, Bin ,  Haspeslagh, Luc

IPC: B81C1/00

CPC classification number: B81C1/00277 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/095

Abstract: A MEMS device 1 is disclosed comprising a cavity 5 containing a MEMS component 6, the cavity 5 being formed in a dielectric layer stack 3 having a thickness t d , whereby the cavity 5 and the dielectric layer stack 3 are sandwiched between a substrate 2 and a sealing dielectric layer 4 having a thickness t s , and whereby the MEMS component 6 is enclosed by at least one trench 8 extending over the thickness t d of the dielectric layer stack 3 and of the sealing dielectric t s .

Abstract translation: 一种MEMS设备1盘游离缺失包含含有微机电系统元件6的空腔5，空腔5被形成为具有厚度TD的电介质层堆叠体3，由此，空洞部5和电介质层堆3被夹在基片2和一个之间 密封电介质层4的厚度TS，并且其中所述MEMS部件6由至少一个沟槽8包围在电介质TS的介电层堆栈3和密封件的厚度TD延伸。