公开(公告)号：US10522438B2

公开(公告)日：2019-12-31

申请号：US15597124

申请日：2017-05-16

Applicant: Industrial Technology Research Institute

Inventor： Chun-Yi Cheng ,  Wei-Yuan Cheng ,  Shu-Wei Kuo ,  Yu-Jhen Yang

IPC: H01L23/31 ,  H01L21/02 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.

公开(公告)号：US20190341373A1

公开(公告)日：2019-11-07

申请号：US16027374

申请日：2018-07-05

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Wei-Yuan Cheng

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/538 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.

公开(公告)号：US09591746B2

公开(公告)日：2017-03-07

申请号：US15199913

申请日：2016-06-30

Applicant: Industrial Technology Research Institute

Inventor： Wei-Yuan Cheng ,  Chen-Chu Tsai ,  Yuh-Zheng Lee

IPC: H05K1/00 ,  H05K3/00 ,  H05K1/02 ,  H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H05K1/11 ,  H05K3/40

CPC classification number: H05K1/028 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16 ,  H01L2924/181 ,  H05K1/0281 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/007 ,  H05K3/4038 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/10106 ,  H05K2201/10128 ,  H05K2201/2009 ,  H05K2203/1178 ,  H01L2924/00012

Abstract: According to embodiments of the disclosure, an electronic device package may include a wire layer and a rigid element. The wire layer includes a first surface and a second surface opposite to each other, and the second surface of the wire layer has at least one coarse structure. A portion of the second surface having the coarse structure has a greater roughness than another portion of the second surface. The rigid element is disposed on the first surface of the wire layer, wherein a stiffness of the rigid element is greater than a stiffness of the wire layer and a projection area of the coarse structure on the first surface of the wire layer overlaps an edge of the rigid element.

Abstract translation: 根据本公开的实施例，电子设备封装可以包括导线层和刚性元件。 线层包括彼此相对的第一表面和第二表面，并且线层的第二表面具有至少一个粗糙结构。 具有粗糙结构的第二表面的一部分具有比第二表面的另一部分更大的粗糙度。 刚性元件设置在线层的第一表面上，其中刚性元件的刚度大于金属丝层的刚度，并且粗糙结构在金属丝层的第一表面上的投影区域与 刚性元素。

公开(公告)号：US09046681B2

公开(公告)日：2015-06-02

申请号：US14033980

申请日：2013-09-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Shu-Wei Kuo ,  Yi-Chun Liu ,  Wei-Yuan Cheng

IPC: G02B26/00

CPC classification number: G02B26/005

Abstract: The disclosure provides an electro-wetting element, including: a first substrate and a second substrate, wherein the first substrate and the second substrate are disposed oppositely; a first electrode formed on the first substrate; a photoreactive layer formed on the first electrode, wherein the photoreactive layer includes a reversible photoreactive material; a second electrode formed on the first substrate or the second substrate; and a polar fluid and a non-polar fluid disposed between the first substrate and the second substrate.

Abstract translation: 本发明提供一种电润湿元件，包括：第一基板和第二基板，其中第一基板和第二基板相对设置; 形成在所述第一基板上的第一电极; 形成在所述第一电极上的光反应层，其中所述光反应层包括可逆光反应性材料; 形成在所述第一基板或所述第二基板上的第二电极; 以及设置在第一基板和第二基板之间的极性流体和非极性流体。

公开(公告)号：US10366965B2

公开(公告)日：2019-07-30

申请号：US15856065

申请日：2017-12-28

Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

Inventor： Shu-Wei Kuo ,  Wei-Yuan Cheng ,  Shau-Fei Cheng

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L23/544 ,  H01L21/67 ,  H01L21/48 ,  H01L23/31

Abstract: A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided.

公开(公告)号：US20190088600A1

公开(公告)日：2019-03-21

申请号：US15849593

申请日：2017-12-20

Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

Inventor： Shu-Wei Kuo ,  Wei-Yuan Cheng ,  Chen-Tsai Yang ,  Jie-Mo Lin

IPC: H01L23/538 ,  H01L23/14 ,  H01L23/15 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.

公开(公告)号：US20180294202A1

公开(公告)日：2018-10-11

申请号：US15856069

申请日：2017-12-28

Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

Inventor： Wei-Yuan Cheng ,  Cheng-Chung Lee ,  Shau-Fei Cheng ,  Wen-Lung Chen

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/60 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a frame disposed around a chip, a filling material filled in the space between the chip and the frame, and a protection layer covering the chip, the frame, and the filling material. The Young's modulus of the filling material is respectively smaller than the Young's modulus of the chip, the Young's modulus of the frame, and the Young's modulus of the protection layer.

公开(公告)号：US11646259B2

公开(公告)日：2023-05-09

申请号：US17159012

申请日：2021-01-26

Applicant: Industrial Technology Research Institute

Inventor： Shu-Wei Kuo ,  Chen-Tsai Yang ,  Wei-Yuan Cheng ,  Chien-Hsun Chu ,  Shau-Fei Cheng

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Provided is a forming method of a redistribution structure including: forming a first redistribution layer and a first compensation circuit layer on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer, and the first compensation circuit layer and the first redistribution layer are electrically insulated from each other; forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; and forming a second redistribution layer and a second compensation circuit layer on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer and the second redistribution layer are electrically insulated from each other, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer.

公开(公告)号：US20200211984A1

公开(公告)日：2020-07-02

申请号：US16404765

申请日：2019-05-07

Applicant: Industrial Technology Research Institute

Inventor： Jui-Chang Chuang ,  Chen-Tsai Yang ,  Wei-Yuan Cheng

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic device package structure and a manufacturing method thereof are provided. The electronic device package structure includes a first electronic device layer, a second electronic device layer, and a filling layer disposed between the first electronic device layer and the second electronic device layer, wherein the Young's modulus of the second electronic device layer is less than or equal to the Young's modulus of the first electronic device layer, and the Young's modulus of the filling layer is less than the Young's modulus of the second electronic device layer, and the ratio of the Young's modulus of the first electronic device layer to the Young's modulus of the filling layer is 10 to 1900 and the ratio of the Young's modulus of the second electronic device layer to the Young's modulus of the filling layer is 7.6 to 1300.

公开(公告)号：US10573587B2

公开(公告)日：2020-02-25

申请号：US15673422

申请日：2017-08-10

Applicant: Industrial Technology Research Institute

Inventor： Shu-Wei Kuo ,  Chun-Yi Cheng ,  Wei-Yuan Cheng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.