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公开(公告)号：JP2006217612A
公开(公告)日：2006-08-17
申请号：JP2006022540
申请日：2006-01-31
Applicant: Infineon Technologies Ag , インフィネオン テクノロジーズ アクチエンゲゼルシャフト
Inventor： ACHARYA PRAMOD
IPC: H03K5/08
CPC classification number: G11C7/225 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C11/4076 , G11C11/4093
Abstract: PROBLEM TO BE SOLVED: To provide a comparator circuit assembly, especially a comparator/receiver circuit assembly and a semiconductor component having such a circuit assembly.
SOLUTION: The comparator/receiver circuit assembly has: first and second transistors (8, 9) in which control input parts are mutually connected; a third transistor (10) connected to the first transistor (8) and in which an input signal (VIN) is applied to a control input part; and a fourth transistor (11) connected to the second transistor (9) and in which a reference signal (VREFmod) is applied to a control input part, wherein the control input part of the third transistor (10) is connected to the first and second transistors (8, 9) via a coupling device (22). The semiconductor component has such a circuit assembly.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：提供比较器电路组件，特别是具有这种电路组件的比较器/接收器电路组件和半导体部件。 解决方案：比较器/接收器电路组件具有：第一和第二晶体管（8,9），其中控制输入部分相互连接; 连接到第一晶体管（8）的第三晶体管（10），其中输入信号（VIN）被施加到控制输入部分; 以及连接到所述第二晶体管（9）的第四晶体管（11），并且其中参考信号（VREFmod）被施加到控制输入部分，其中所述第三晶体管（10）的控制输入部分连接到所述第一晶体管 第二晶体管（8,9）经由耦合器件（22）。 半导体部件具有这样的电路组件。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：DE102005026195A1
公开(公告)日：2006-01-05
申请号：DE102005026195
申请日：2005-06-07
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ACHARYA PRAMOD
Abstract: The invention is aimed at providing a novel semi-conductor component, as well as a novel process for reading test data. There is a process for reading test data is made available, including reading test data generated during a semi-conductor component test procedure from at least one test data register of a semi-conductor component, storing the test data in at least one useful data memory cell provided on the semi-conductor component, and reading the test data from the at least one useful data memory cell.
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公开(公告)号：DE10208715A1
公开(公告)日：2003-09-18
申请号：DE10208715
申请日：2002-02-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHROEGMEIER PETER , DIETRICH STEFAN , KIESER SABINE , ACHARYA PRAMOD
IPC: G11C7/10 , G11C7/22 , G11C11/4076
Abstract: The device produces a time-delayed data release signal and has a controllable latency time generator for time delay of a decoded external data release signal with an adjustable latency time. A comparison circuit compares a cycle time for the high frequency clock signal with a predefined signal transition time for the data path and reduces the latency time generator latency time by the cycle time if the signal transition time exceeds the cycle time. The device produces a time-delayed data release signal for time-synchronous data transfer via a S-DRAM data path and has a controllable latency time generator (57) for time delay of a decoded external data release signal with an adjustable latency time. A comparison circuit (60) compares a cycle time for the high frequency clock signal (CLK) with a predefined signal transition time for the data path and reduces latency time of the latency time generator by the cycle time if the signal transition time exceeds the cycle time.
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公开(公告)号：DE102008023126B4
公开(公告)日：2012-08-30
申请号：DE102008023126
申请日：2008-05-09
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ACHARYA PRAMOD , KAIDALA RAVI KIRAN , KASHINKUNTI PRASHANT
IPC: H03K19/00
Abstract: Schaltkreis, der folgendes umfasst: einen an eine erste Versorgungsspannung (VSS) gekoppelten Anschluss (201); einen geschalteten Bus (210; 315), der mehrere Knoten umfasst; mehrere Schalter (220; 318), wobei jeder einzelne der Schalter (220; 318) zwischen einen der Knoten und den Anschluss (201) gekoppelt ist, eine an den geschalteten Bus (210; 315) gekoppelte Spannungsdetektorschaltung (250; 360) zum Detektieren der Spannung des geschalteten Busses (210; 315), und eine an den geschalteten Bus (210; 315) gekoppelte Thyristorschaltung, wobei der Schaltkreis ausgelegt ist, einen der folgenden Zustände einzunehmen: einen verbundenen Zustand, in dem alle Schalter geschlossen sind; einen getrennten Zustand, in dem alle Schalter offen sind, und lossen und zweite Schalter offen sind, und wobei während des verbundenen Zustands die Thyristorschaltung eine der ersten Versorgungsspannung (VSS) entsprechende erste Ausgangsspannung (TIE0) und eine einer zweiten Versorgungsspannung (VDD) entsprechende zweite Ausgangsspannung...
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公开(公告)号：DE19955775C2
公开(公告)日：2002-04-18
申请号：DE19955775
申请日：1999-11-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ACHARYA PRAMOD , TAEUBER ANDREAS
IPC: G05F1/46 , G05F1/10 , G11C5/14 , G11C11/4074 , H01L27/108
Abstract: The voltage supply provides voltages to an electronic circuit requiring at least two different supply voltages. A plurality of standby supply voltages with different levels are obtained from the highest supply voltage with the aid of a voltage divider.
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Patent Agency Ranking
公开(公告)号：DE10001648C2
公开(公告)日：2002-03-14
申请号：DE10001648
申请日：2000-01-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ACHARYA PRAMOD , TAEUBER ANDREAS
IPC: G11C11/407 , G11C5/14 , G11C7/10 , G11C11/4074
Abstract: An integrated circuit containing a number of subcircuits is described. Each of the subcircuits contains a driver circuit for driving in each case one controllable voltage source on the basis of a reference value. The driver circuit has a memory unit for storing a reference value and a terminal for outputting a first reference value or for inputting a second reference value. A signal line, which is used for transmitting a signal, is connected to the terminal of the driver circuit of each of the subcircuits. The driving by the driver circuit is effected in each subcircuit on the basis of a common reference value that is transmitted via the signal line. Thus, the time needed for setting the reference values for all subcircuits is relatively short.
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公开(公告)号：DE102008023126A1
公开(公告)日：2008-11-20
申请号：DE102008023126
申请日：2008-05-09
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ACHARYA PRAMOD , KAIDALA RAVI KIRAN , KASHINKUNTI PRASHANT
IPC: H03K19/00
Abstract: The cell based integrated circuit (100) for use with a library of basic modules, has two supply voltage connections and a standard cell (10), which has a thyristor circuit (20). Two entrances are provided for entering supply voltages, and two exits are provided, where former exit spends former supply voltage appropriate to an output voltage and latter exit for spending latter supply voltage appropriate to another output voltage. The thyristor circuit has two metal oxide semiconductor transistors. Independent claims are also included for the following: (1) a method for operation of a thyristor circuit and a logic gate circuit in a standard cell of a cell-based integrated circuit (2) a circuit, which has a connection coupled to a supply voltage (3) a method for switching a connection between two connections.
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公开(公告)号：DE10208715B4
公开(公告)日：2004-05-06
申请号：DE10208715
申请日：2002-02-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHROEGMEIER PETER , DIETRICH STEFAN , KIESER SABINE , ACHARYA PRAMOD
IPC: G11C7/10 , G11C7/22 , G11C11/4076
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公开(公告)号：DE10203893A1
公开(公告)日：2003-09-25
申请号：DE10203893
申请日：2002-01-31
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHROEGMEIER PETER , DIETRICH STEFAN , KIESER SABINE , ACHARYA PRAMOD
IPC: G11C7/10 , G11C11/4093 , G11C7/22 , G11C11/407
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公开(公告)号：DE10208716A1
公开(公告)日：2003-09-18
申请号：DE10208716
申请日：2002-02-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHROEGMEIER PETER , DIETRICH STEFAN , KIESER SABINE , ACHARYA PRAMOD , WEIS CHRISTIAN
IPC: G11C7/10 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4096 , G11C11/407
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