公开(公告)号：JP2002319284A

公开(公告)日：2002-10-31

申请号：JP2002079611

申请日：2002-03-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  SCHROEGMEIER PETER ,  KIESER SABINE ,  WEIS CHRISTIAN

IPC: G11C11/417 ,  G06F13/40 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H04L25/49

Abstract: PROBLEM TO BE SOLVED: To provide a data transmitting method which improves data transmission band width of a transmission path related to a semiconductor memory, while being simple and maintaining reliability. SOLUTION: A first multiplexer/demultiplexer 12 encodes data sequence and generates data signal of an appropriate current/voltage level for data transmission on an internal data transmission path 10 of a semiconductor memory. Then the signal is transmitted, in synchronization with a clock signal using the transmission path 10. After the second multiplexer/demultiplexer 13 receives data signal, and data sequence is led out by assessing the current/voltage level.

公开(公告)号：DE10208715A1

公开(公告)日：2003-09-18

申请号：DE10208715

申请日：2002-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  KIESER SABINE ,  ACHARYA PRAMOD

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076

Abstract: The device produces a time-delayed data release signal and has a controllable latency time generator for time delay of a decoded external data release signal with an adjustable latency time. A comparison circuit compares a cycle time for the high frequency clock signal with a predefined signal transition time for the data path and reduces the latency time generator latency time by the cycle time if the signal transition time exceeds the cycle time. The device produces a time-delayed data release signal for time-synchronous data transfer via a S-DRAM data path and has a controllable latency time generator (57) for time delay of a decoded external data release signal with an adjustable latency time. A comparison circuit (60) compares a cycle time for the high frequency clock signal (CLK) with a predefined signal transition time for the data path and reduces latency time of the latency time generator by the cycle time if the signal transition time exceeds the cycle time.

公开(公告)号：DE10203893B4

公开(公告)日：2004-01-15

申请号：DE10203893

申请日：2002-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  KIESER SABINE ,  ACHARYA PRAMOD

IPC: G11C7/10 ,  G11C11/4093 ,  G11C7/22 ,  G11C11/407

公开(公告)号：DE10203152C1

公开(公告)日：2003-10-23

申请号：DE10203152

申请日：2002-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  ACHARYA PRAMOD ,  KIESER SABINE ,  GRAESSER URSULA ,  SCHNEIDER HELMUT ,  MARKERT MICHAEL

IPC: G11C8/08 ,  H01L27/108 ,  H01L27/105

Abstract: The memory device (100) has at least one memory module and associated word decoder block and at least one driver transistor pair (101a,101b), coupled to the word decoder block at their gates (104) in a ring structure (RDC). The sources (102) of the driver transistor pair lie outside the ring structure and have a common diffusion zone, the drains lying within the ring structure and coupled to at least one memory row selection line (106a,106b), adjacent selection lines coupled via a coupling transistor (105) receiving the same gate signal as the driver transistor pair.

公开(公告)号：DE10154066A1

公开(公告)日：2003-05-22

申请号：DE10154066

申请日：2001-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  KIESER SABINE ,  WEIS CHRISTIAN ,  MARKERT MICHAEL ,  HEIN THOMAS

IPC: G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/10

Abstract: The memory has a cell field with row lines for cell selection, column lines for reading or writing data signals via read-write amplifiers and column selection lines for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads. A control circuit activates at least 2 different column selection lines with one column address and one of the column lines for 2 or more column addresses. The device has a memory cell field with row lines (WL1-4) for selecting cells and column lines for reading or writing data signals via read-write amplifiers (11,12,21,22) and column selection lines (CSL1,2) for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads (15,25). A control circuit activates at least two different column selection lines with one column address and one of the column lines for two or more column addresses. AN Independent claim is also included for the following: a method of operating an inventive device.

公开(公告)号：FR2822581A1

公开(公告)日：2002-09-27

申请号：FR0203604

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  SCHROGMEIER PETER ,  KIESER SABINE ,  WEIS CHRISTIAN

IPC: G11C11/417 ,  G06F13/40 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H04L25/49 ,  H03K19/00 ,  H04B1/69

Abstract: The method involves coding a data sequence by defining a current level and a voltage level for a data signal which is then transferred. The data signal is then decoded by evaluating the current and voltage levels to determine the data sequence transferred in data signal. An Independent claim is included for data transfer device.

公开(公告)号：DE10210726B4

公开(公告)日：2005-02-17

申请号：DE10210726

申请日：2002-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  KIESER SABINE ,  ARCHARYA PRAMOD

IPC: G11C7/10 ,  H03L7/081 ,  G11C11/4076 ,  G11C7/22

Abstract: Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.

公开(公告)号：DE10154066B4

公开(公告)日：2004-02-12

申请号：DE10154066

申请日：2001-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  KIESER SABINE ,  WEIS CHRISTIAN ,  MARKERT MICHAEL ,  HEIN THOMAS

IPC: G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/10

Abstract: The memory has a cell field with row lines for cell selection, column lines for reading or writing data signals via read-write amplifiers and column selection lines for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads. A control circuit activates at least 2 different column selection lines with one column address and one of the column lines for 2 or more column addresses. The device has a memory cell field with row lines (WL1-4) for selecting cells and column lines for reading or writing data signals via read-write amplifiers (11,12,21,22) and column selection lines (CSL1,2) for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads (15,25). A control circuit activates at least two different column selection lines with one column address and one of the column lines for two or more column addresses. AN Independent claim is also included for the following: a method of operating an inventive device.

公开(公告)号：DE10210726A1

公开(公告)日：2003-10-16

申请号：DE10210726

申请日：2002-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  KIESER SABINE ,  ARCHARYA PRAMOD

IPC: G11C7/10 ,  H03L7/081 ,  G11C7/22

Abstract: Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.

公开(公告)号：FR2822581B1

公开(公告)日：2006-05-12

申请号：FR0203604

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  SCHROGMEIER PETER ,  KIESER SABINE ,  WEIS CHRISTIAN

IPC: G11C7/10 ,  G11C11/417 ,  G06F13/40 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H03K19/00 ,  H03M7/30 ,  H04B1/69 ,  H04L25/49

Abstract: Data transfer is effected on an internal and/or on an external transfer path with or in a semiconductor component, such as a semiconductor memory. A first multiplexer/demultiplexer codes a data sequence by defining a current level and a voltage level for a data signal. The coded sequence is then transferred on the transfer path synchronously with a clock signal and is decoded in a second multiplexer/demultiplexer by evaluation of the received current level and of the received voltage level. From this, the transferred data sequence is determined.