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    DATA TRANSMITTING METHOD AND DEVICE
    1.
    发明专利
    DATA TRANSMITTING METHOD AND DEVICE 审中-公开

    公开(公告)号：JP2002319284A

    公开(公告)日：2002-10-31

    申请号：JP2002079611

    申请日：2002-03-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETRICH STEFAN ,  SCHROEGMEIER PETER ,  KIESER SABINE ,  WEIS CHRISTIAN

    IPC: G11C11/417 ,  G06F13/40 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H04L25/49

    Abstract: PROBLEM TO BE SOLVED: To provide a data transmitting method which improves data transmission band width of a transmission path related to a semiconductor memory, while being simple and maintaining reliability. SOLUTION: A first multiplexer/demultiplexer 12 encodes data sequence and generates data signal of an appropriate current/voltage level for data transmission on an internal data transmission path 10 of a semiconductor memory. Then the signal is transmitted, in synchronization with a clock signal using the transmission path 10. After the second multiplexer/demultiplexer 13 receives data signal, and data sequence is led out by assessing the current/voltage level.

    MEMORY DEVICE
    2.
    发明专利
    MEMORY DEVICE 审中-公开

    公开(公告)号：JP2006351014A

    公开(公告)日：2006-12-28

    申请号：JP2006164490

    申请日：2006-06-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WEIS CHRISTIAN ,  KALMS SVEN ,  RUCKERBAUER HERMANN

    IPC: G06F12/16 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16

    Abstract: PROBLEM TO BE SOLVED: To provide a memory device having an ECC function further easily understandable and having a simple architecture. SOLUTION: This memory device is provided with at least two DRAM memory modules, at least one external ECC module and a memory controller. The external ECC module provides the ECC function to the memory modules. The respective memory modules are connected to the memory controller through memory channels corresponding to them. The plurality of external ECC modules are connected to the memory controller through one shared ECC channel. Each external ECC module is allocated to one group comprising the plurality of memory modules. The plurality of memory modules of the one group having the respective ECC modules are operated in synchronization with one another by the memory controller. COPYRIGHT: (C)2007,JPO&INPIT

    INTEGRATED CIRCUIT EQUIPPED WITH COMMAND DECODER
    3.
    发明专利
    INTEGRATED CIRCUIT EQUIPPED WITH COMMAND DECODER 失效

    公开(公告)号：JP2001052478A

    公开(公告)日：2001-02-23

    申请号：JP2000188221

    申请日：2000-06-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHROEGEMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN

    IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

    Abstract: PROBLEM TO BE SOLVED: To make improvements so that none of the output sides of command decoders concerns activation by not activating the output side of a command decoder when a nonactivation command is supplied to its input side and activating the output side of the command decoder when a command different from the nonactivation command is supplied to its input side. SOLUTION: A command decoder CDEC activates its output side CMDi by commands supplied to itself except a case that the nonactivation command DEACT=1110 is supplied. With this nonactivation command DEACT=1110, the command decoder CDEC does not activates its output side CMDi. Consequently, no internal command signal is activated and a memory performs no operation. An activation decoder ADEC sends commands applied to respective input sides from the output side as they are always without changing them with an activation signal/CS=O.

    VOLTAGE PUMP WITH THROW-IN CONTROL MECHANISM
    5.
    发明专利
    VOLTAGE PUMP WITH THROW-IN CONTROL MECHANISM 审中-公开

    公开(公告)号：JP2002186247A

    公开(公告)日：2002-06-28

    申请号：JP2001322789

    申请日：2001-10-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETRICH STEFAN ,  HEYNE PATRICK ,  MARX THILO ,  SCHOENIGER SABINE ,  SOMMER MICHAEL ,  HEIN THOMAS ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

    IPC: H02M3/07

    Abstract: PROBLEM TO BE SOLVED: To provide a voltage pump with a throw-in control mechanism in which the operation is stable at the time of increasing supply voltage and the output voltage being pumped is prepared as quickly as possible. SOLUTION: The voltage pump 7 for generating an increased output voltage is provided with a throw-in control mechanism having a transistor 1 connected between a terminal 3 for introducing a supply voltage and a terminal 4 for taking out an increased output voltage. Upon starting operation of the voltage pump 7, the increased output voltage is interrupted from the supply voltage through the transistor 1. A switch 2 transfers the higher one of the output voltage or the supply voltage to a substrate terminal and a gate terminal of the transistor 1, respectively. The throw-in control mechanism allows standby at the early state of increased output voltage in the safety rising operation of the voltage pump 7 without requiring a significant circuit cost.

    INTEGRATED CIRCUIT
    6.
    发明专利
    INTEGRATED CIRCUIT 失效

    公开(公告)号：JP2001035163A

    公开(公告)日：2001-02-09

    申请号：JP2000195059

    申请日：2000-06-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETRICH STEFAN ,  SCHROEGEMEIER PETER ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN

    IPC: G11C11/408 ,  G11C8/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413

    Abstract: PROBLEM TO BE SOLVED: To optimize a decoding speed corresponding to each of operating modes by performing different kinds of decoding respectively in various operating modes. SOLUTION: This circuit has a first decoder unit D1 and a second decoder unit D2 parallel connected thereto, each of two decoder units respectively has one input side to supply input signals A0...A2 to be decoded and (n) output sides, the relevant decoder unit makes (n) output sides active while depending on the input signals and decodes the input signals with various methods, the input side of the second decoder unit is connected to one input side of the first decoder unit D1, further, this circuit has (n) lines L1 to be selected, the line to be selected is connected with one output side of each of two decoder units and the potential of the line to be selected is detected through the output side by the first decoder unit in the first operating mode and by the second decoder unit in the second operating mode.

    INTEGRATED MEMORY
    7.
    发明专利
    INTEGRATED MEMORY 失效

    公开(公告)号：JP2001035162A

    公开(公告)日：2001-02-09

    申请号：JP2000190006

    申请日：2000-06-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETRICH STEFAN ,  MUSA SAGLAM ,  SCHROEGEMEIER PETER ,  MARKERT MICHAEL ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN

    IPC: G11C11/408 ,  G11C7/00 ,  G11C8/00 ,  G11C8/10 ,  G11C11/401

    Abstract: PROBLEM TO BE SOLVED: To obtain an activation time having an approximately same length with respect to a first selection line of first and second groups by providing the situation in which first and second address paths have first and second lines and first and second decoder circuits, the first decoder circuit decodes a supplied address faster than the second decoder circuit and the first line has a longer signal progressing time than the second line. SOLUTION: An address terminal ADR is connected to column selection lines CSL of first and second groups G1 and G2 through first and second address paths made up with first and second lines L1 and L2 and first and second decoder circuits DEC1 and DECK. The speed of the circuit DEC2 is slower than the speed of the circuit DEC1. By making the total length of the line L2 to be longer than the total length of the line L1, the signal progressing time of the line L1 becomes longer than the signal progressing time of the line L2 and the difference in the decoding time of the circuits DEC1 and DEC2 is compensated for.

    8.
    发明专利
    未知

    公开(公告)号：DE50113577D1

    公开(公告)日：2008-03-27

    申请号：DE50113577

    申请日：2001-05-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETRICH STEFAN DR ,  SCHOENIGER SABINE ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

    IPC: G11C8/00 ,  G11C8/08

    Abstract: An integrated memory has memory cells which are each connected to a row line to select one of the memory cells and to a column line to read or write a data signal. A row access controller is used to activate one of the row lines to select one of the memory cells and to control a precharging operation to precharge one of the row lines. A precharge command initiates a precharging operation. The precharging operation for an activated row line is triggered by the row access controller when the reading or writing of a data signal has been finished and when a defined time interval, during which the row line must at least be activated, has elapsed since the activation. As a result, a precharging operation of the activated row line is controlled in a self-adjusting manner. A method of operating an integrated memory is also provided.

    9.
    发明专利
    未知

    公开(公告)号：DE19929172B4

    公开(公告)日：2006-12-28

    申请号：DE19929172

    申请日：1999-06-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN ,  MARKERT MICHAEL ,  MUSA SAGLAM

    IPC: G11C8/00 ,  G11C11/408 ,  G11C7/00 ,  G11C8/10 ,  G11C11/401

    Abstract: The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.

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