公开(公告)号：DE59814274D1

公开(公告)日：2008-10-02

申请号：DE59814274

申请日：1998-11-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  AEUGLE THOMAS DR ,  ROESNER WOLFGANG DR ,  RISCH LOTHAR DR

IPC: H01L27/11 ,  G11C11/40 ,  H01L21/8244

Abstract: The cell arrangement includes at least six transistors per memory cell. Four of the transistors form a flip-flop and are arranged at corners of a square. The flip-flop is controlled by two of the transistors which are respectively arranged adjacent on diagonally opposite corners of the square. Memory cells adjacent along a word conductor can be arranged in such a way, that a first bit conductor and a second bit conductor of the adjacent memory cells coincide. The transistors are arranged preferably vertically and in semiconductor structures which are produced by a layer sequence. Two of the transistors with n-endowed channel areas, are preferably formed in two separate semiconductor structures.