公开(公告)号：DE59814274D1

公开(公告)日：2008-10-02

申请号：DE59814274

申请日：1998-11-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  AEUGLE THOMAS DR ,  ROESNER WOLFGANG DR ,  RISCH LOTHAR DR

IPC: H01L27/11 ,  G11C11/40 ,  H01L21/8244

Abstract: The cell arrangement includes at least six transistors per memory cell. Four of the transistors form a flip-flop and are arranged at corners of a square. The flip-flop is controlled by two of the transistors which are respectively arranged adjacent on diagonally opposite corners of the square. Memory cells adjacent along a word conductor can be arranged in such a way, that a first bit conductor and a second bit conductor of the adjacent memory cells coincide. The transistors are arranged preferably vertically and in semiconductor structures which are produced by a layer sequence. Two of the transistors with n-endowed channel areas, are preferably formed in two separate semiconductor structures.

公开(公告)号：AT222403T

公开(公告)日：2002-08-15

申请号：AT96107434

申请日：1996-05-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG DR ,  RISCH LOTHAR DR ,  HOFMANN FRANZ DR ,  KRAUTSCHNEIDER WOLFGANG DR

IPC: H01L21/8242 ,  H01L27/108

Abstract: In a DRAM cell arrangement with memory cells, each consisting of a read-out transistor and a storage capacitor, the novelty is that (a) the read-out transistor is a vertical MOS transistor which is integrated in a semiconductor substrate (2) and has one source/drain region (3) adjoining a main substrate face (1), the other source/drain region (5) adjoining a buried bit line (5) and the gate electrode (13) connected to a buried word line crossing the bit line (5); and (b) the storage capacitor is formed of a source/drain region (3) (as memory node) adjacent the main face (1), an overlying capacitor dielectric (16) and a capacitor plate (17). Also claimed is a method of producing the DRAM cell arrangement.

公开(公告)号：AT205019T

公开(公告)日：2001-09-15

申请号：AT96107433

申请日：1996-05-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG DR ,  RISCH LOTHAR DR ,  HOFMANN FRANZ DR ,  KRAUTSCHNEIDER WOLFGANG DR

IPC: H01L21/8242 ,  H01L27/108

Abstract: For each storage cell, the DRAM cell arrangement has a vertical MOS transistor, the first source/drain region of which is connected to a memory node of a storage capacitor, the channel region of which is annularly enclosed by a gate electrode and the second source/drain region of which is connected to a buried bit line. The DRAM cell arrangement can be produced with a storage-cell area of 4F2 by using only two masks, F being the minimum producible structure size in the respective technology.