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1.发明申请METHOD AND CIRCUIT FOR GENERATING ADDRESSES OF PSEUDO-RANDOM INTERLEAVERS OR DEINTERLEAVERS 审中-公开方法与电路地址产生伪随机的或交织-DEINTERLEAVERN
公开(公告)号：WO2004073167A3
公开(公告)日：2006-02-02
申请号：PCT/DE2004000167
申请日：2004-02-03
Applicant: INFINEON TECHNOLOGIES AG , HERNDL THOMAS , BERKMANN JENS
Inventor： HERNDL THOMAS , BERKMANN JENS
CPC classification number: H03M13/2957 , H03M13/2714 , H03M13/2764 , H03M13/2771 , H03M13/2789 , H04L1/0043 , H04L1/0066
Abstract: According to the invention, a pair of coordinates (c1, r1) of a rectangular matrix is calculated for a certain index k of an interleaved or deinterleaved sequence of symbols. Said pair of coordinates is corrected so as to take into account fillers in the rectangular matrix. A transformed pair of coordinates (c6, r6) is determined for the corrected pair of coordinates (c4, r5) by means of a matrix coordinate transformation (T1) process. A valid interleaving address or deinterleaving address I (k) is then calculated from the transformed pair of coordinates (c6, r6) at a timing step k.
Abstract translation: 在某个索引锁定或交错码元序列中的k的方阵的一对坐标（C1，R1）进行计算。 坐标对被校正以考虑填充字符的矩形矩阵。 它是一个变换通过执行计算校正后的坐标对的矩阵的坐标变换（T1）坐标对（C6，R6）（，R5 C4）。 随后的时间步骤k从转化的坐标对（C6，R6）的计算有效的交织或解交织地址I（K）。
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公开(公告)号：DE102008056602A1
公开(公告)日：2009-05-20
申请号：DE102008056602
申请日：2008-11-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BOTTERO MAURO , BERKMANN JENS
IPC: H03M13/41
Abstract: A method for detection of a control channel includes receiving data transmitted via the control channel. A control channel receive quality is estimated based on a metric difference between a metric of a known final trellis state and a minimum metric amongst the metrics of the trellis states based on the received data. It is decided whether or not to detect the control channel depending on the estimated control channel receive quality.
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公开(公告)号：DE10328077B3
公开(公告)日：2005-05-04
申请号：DE10328077
申请日：2003-06-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BERKMANN JENS , RUPRICH THOMAS
Abstract: The receiver synchronization method provides transmission time interval synchronization by repetitive checking of the reception signal for detection of a synchronization time slot within a signal structure contained in the reception signal, the maximum number of repetitions being greater than the number of possible synchronization time slots within the signal structure, the actual number of repetitions controlled by an interrupt condition (3).
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公开(公告)号：DE10310812A1
公开(公告)日：2004-10-28
申请号：DE10310812
申请日：2003-03-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HERNDL THOMAS , BERKMANN JENS , BECKER BURKHARD
Abstract: A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.
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公开(公告)号：DE10238841B4
公开(公告)日：2010-01-28
申请号：DE10238841
申请日：2002-08-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BERKMANN JENS , HAEUTLE ARMIN , HAAS WOLFGANG , SIMEUNOVIC SASHA , HODITS GERALD , HERNDL THOMAS
Abstract: Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.
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Patent Agency Ranking
公开(公告)号：DE10328340B4
公开(公告)日：2005-05-04
申请号：DE10328340
申请日：2003-06-24
Applicant: INFINEON TECHNOLOGIES AG
Inventor： NIEDERHOLZ JUERGEN , BECKER BURKHARD , SPETH MICHAEL , BERKMANN JENS , ZIMMERMANN MANFRED
Abstract: The method involves the computation of a data channel by path weights for a data signal in a receiver and computing an uncorrected path weight for the data signal transmitted over a regulated data channel using a common pilot channel (CPICH). The uncorrected path weight is corrected by multiplication of a correction factor which contains the relationship of a data channel-specific reinforcement estimation to a pilot-channel-based reinforcement estimation. - An INDEPENDENT CLAIM is included for a device for the computation of a data channel regulated by path weights of a data signal
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公开(公告)号：DE10306302A1
公开(公告)日：2004-08-26
申请号：DE10306302
申请日：2003-02-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HERNDL THOMAS , BERKMANN JENS
Abstract: The method involves calculating a coordinate pair of a square matrix, in dependence on k. The coordinate pair is corrected to allow for fill characters (d). The transformed coordinate pair is determined from the corrected coordinate pair by matrix-coordinate transformation. A valid interleaving or de-interleaving address is calculated from the transformed coordinate pair in accordance with the writing allocation rule. Independent claims are included for : (1) an apparatus for calculating interleaving and de-interleaving addresses; (2) a turbo decoder; and (3) a turbo encoder.
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公开(公告)号：DE10238841A1
公开(公告)日：2004-03-11
申请号：DE10238841
申请日：2002-08-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BERKMANN JENS , HAEUTLE ARMIN , HAAS WOLFGANG , SIMEUNOVIC SASHA , HODITS GERALD , HERNDL THOMAS
Abstract: Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.
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公开(公告)号：DE102009044555A1
公开(公告)日：2010-05-20
申请号：DE102009044555
申请日：2009-11-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WANG XIAO-AN , BERKMANN JENS
IPC: H03M13/09
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公开(公告)号：DE10310812B4
公开(公告)日：2007-11-22
申请号：DE10310812
申请日：2003-03-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HERNDL THOMAS , BERKMANN JENS , BECKER BURKHARD
Abstract: A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.
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