公开(公告)号：DE10238841B4

公开(公告)日：2010-01-28

申请号：DE10238841

申请日：2002-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERKMANN JENS ,  HAEUTLE ARMIN ,  HAAS WOLFGANG ,  SIMEUNOVIC SASHA ,  HODITS GERALD ,  HERNDL THOMAS

IPC: H03M13/09 ,  H04B7/26 ,  H04L1/00 ,  H04L1/20 ,  H04W84/06

Abstract: Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.

公开(公告)号：DE10238841A1

公开(公告)日：2004-03-11

申请号：DE10238841

申请日：2002-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERKMANN JENS ,  HAEUTLE ARMIN ,  HAAS WOLFGANG ,  SIMEUNOVIC SASHA ,  HODITS GERALD ,  HERNDL THOMAS

IPC: H03M13/09 ,  H04L1/00 ,  H04Q7/20 ,  H04B7/26 ,  H04L1/20

Abstract: Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.