公开(公告)号：DE10345383A1

公开(公告)日：2004-04-15

申请号：DE10345383

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOWYER STEPHEN ,  LE THOAI-THAI

IPC: G06F1/32 ,  G06F12/00 ,  G06F12/06 ,  G06F12/08 ,  G11C11/406

Abstract: A system and method for refreshing data in a dynamic random access memory ("DRAM") is provided, where the system includes a data memory having a plurality of memory banks, a map memory in signal communication with the data memory for translating an internal address of each of the plurality of memory banks into a corresponding external address, a map comparator in signal communication with the map memory for selectively enabling a memory bank in accordance with its external address, a refresh address generator in signal communication with the map comparator for selectively refreshing the enabled memory bank in accordance with its external address, and a refresh counter in signal communication with the refresh address generator for signaling a refresh in accordance with the maximum required refresh time of the enabled memory bank; and where the corresponding method includes determining the maximum required refresh period for each of the memory banks, respectively, prioritizing the memory banks in accordance with their respective refresh periods, utilizing the memory banks in order of their respective prioritizations, selectively disabling at least one of the memory banks in reverse-order of their respective prioritizations, and refreshing only the remaining non-disabled memory banks.

公开(公告)号：DE102006007326A1

公开(公告)日：2006-08-24

申请号：DE102006007326

申请日：2006-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOWYER STEPHEN ,  DANIEL ALAN

IPC: G11C29/52 ,  G06F11/08 ,  G06F11/10

Abstract: The circuit has a data memory (52) to receive and store a data, and a write tree (56) to receive the data and produce a parity data. A parity memory (54) receives and holds the parity data. A read tree (58) receives the data from the data memory and thee parity data from the parity memory. The read tree also produces a display, whether an error is occurred in the data during storage within the data memory. Independent claims are also included for the following: (1) an application housing with an application chip and a evidently good chip (2) a memory device with a data memory (3) a method for detecting an error in a memory device (4) a method for manufacturing an application housing (5) a error correction method.

公开(公告)号：DE10345383B4

公开(公告)日：2007-10-04

申请号：DE10345383

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOWYER STEPHEN ,  LE THOAI-THAI

IPC: G11C11/406 ,  G06F1/32 ,  G06F12/00 ,  G06F12/06 ,  G06F12/08

Abstract: A system and method for refreshing data in a dynamic random access memory ("DRAM") is provided, where the system includes a data memory having a plurality of memory banks, a map memory in signal communication with the data memory for translating an internal address of each of the plurality of memory banks into a corresponding external address, a map comparator in signal communication with the map memory for selectively enabling a memory bank in accordance with its external address, a refresh address generator in signal communication with the map comparator for selectively refreshing the enabled memory bank in accordance with its external address, and a refresh counter in signal communication with the refresh address generator for signaling a refresh in accordance with the maximum required refresh time of the enabled memory bank; and where the corresponding method includes determining the maximum required refresh period for each of the memory banks, respectively, prioritizing the memory banks in accordance with their respective refresh periods, utilizing the memory banks in order of their respective prioritizations, selectively disabling at least one of the memory banks in reverse-order of their respective prioritizations, and refreshing only the remaining non-disabled memory banks.

公开(公告)号：DE102004061313A1

公开(公告)日：2005-07-21

申请号：DE102004061313

申请日：2004-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOWYER STEPHEN ,  EGERER JENS ,  KIM JUNG PILL

IPC: H03B5/04 ,  H03B5/08 ,  H03L1/02 ,  H03L7/00