公开(公告)号：JP2000315387A

公开(公告)日：2000-11-14

申请号：JP2000113867

申请日：2000-04-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  TRUNK ANDREA ,  PFEFFERL KARL-PETER

IPC: G11C8/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/408

Abstract: PROBLEM TO BE SOLVED: To obtain a semiconductor memory having memory banks in which a design cost for a memory bank decoder is small. SOLUTION: In a semiconductor memory having memory banks, plural memory banks are operated by a memory bank decoder. Even if two groups of the memory bank are controlled through the same memory bank decoder, switching between the memory bank decoders is performed by using a pre- decoder. Thereby, layout of the memory bank decoder having comparatively small memory capacity can be succeeded to memories of memory bank decoder having comparatively large capacity.

公开(公告)号：JP2001229676A

公开(公告)日：2001-08-24

申请号：JP2001004181

申请日：2001-01-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  KUHNE SEBASTIAN ,  LE THOAI-THAI

IPC: G11C11/409 ,  G11C11/407 ,  H03F3/45 ,  H03K19/0944

Abstract: PROBLEM TO BE SOLVED: To improve an integrated circuit by selecting a MOS transistor and supplying stable voltage. SOLUTION: A differential amplifier 1 has two input transistors T1, T2, a load element 2, and a current source 3 having a N channel MOS transistor T3, a section to be controlled of the transistor is connected to an input transistor and a current source supply connection terminal 31, and a control connection terminal G is connected to a connection terminal of a potential V3 being positive for a reference potential GND. An integrated circuit is inclined in a circuit device of a dynamic memory, the supply connection terminal of the current source is connected to a voltage source 4 for cutting off an array panel transistor of an integrated dynamic memory, and the voltage source has a negative potential V2 for the reference potential.

公开(公告)号：JP2006203211A

公开(公告)日：2006-08-03

申请号：JP2006011352

申请日：2006-01-19

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： LE THOAI-THAI ,  OH JONG-HOON

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To prevent an interconnection portion from being made longer, while making a module thinner, in an integrated circuit chip laminated multi-chip module. SOLUTION: A multi-chip module (MCM) is provided with a first integrated circuit 310, a second integrated circuit 320, and a bridge layer 330, in at least one upper side of the second integrated circuit 320. The bridge layer 330 forms a signal path between the first contact section 331 of the bridge layer 330 and the second contact section 336 of the bridge layer 330. In order to transmit a signal from the first integrated circuit 310 to the outside of a package 340 and/or to receive the signal from the outside of the package 340 to the first integrated circuit 310, the bridge layer 330 forms the signal path between the first contact section 331 of the bridge layer 330 and an input/output (I/O) circuit element of the second integrated circuit 320, and also forms the signal path between the I/O circuit element of the second integrated circuit 320 and the second contact section 336 of the bridge layer 330. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了防止在集成电路芯片层叠多芯片模块中使互连部分变得更长，同时使模块更薄。 解决方案：多芯片模块（MCM）在第二集成电路320的至少一个上侧设置有第一集成电路310，第二集成电路320和桥接层330.桥接层 330形成了桥接层330的第一接触部分331和桥接层330的第二接触部分336之间的信号路径。为了将信号从第一集成电路310传输到封装340的外部和/或 为了将信号从封装340的外部接收到第一集成电路310，桥接层330形成桥接层330的第一接触部分331与第一接触部分331之间的信号路径，以及桥接层330的输入/输出（I / O）电路元件 第二集成电路320，并且还形成第二集成电路320的I / O电路元件和桥接层330的第二接触部分336之间的信号路径。（C）2006年，JPO和NCIPI

公开(公告)号：JP2002093172A

公开(公告)日：2002-03-29

申请号：JP2001200241

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRASS ECKHARD ,  LE THOAI-THAI ,  LINDOLF JUERGEN ,  SCHNABEL JOACHIM

IPC: G11C11/409 ,  G11C5/14 ,  G11C7/06 ,  G11C7/22 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To supply or introduce control voltage caused by a refresh-current to differential amplifiers functioning as receivers respectively in order to introduce a right operation point. SOLUTION: A receiver circuit, especially, parts arranged in a circuit for switching between a standby mode and an operation mode.

公开(公告)号：DE10345383B4

公开(公告)日：2007-10-04

申请号：DE10345383

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOWYER STEPHEN ,  LE THOAI-THAI

IPC: G11C11/406 ,  G06F1/32 ,  G06F12/00 ,  G06F12/06 ,  G06F12/08

Abstract: A system and method for refreshing data in a dynamic random access memory ("DRAM") is provided, where the system includes a data memory having a plurality of memory banks, a map memory in signal communication with the data memory for translating an internal address of each of the plurality of memory banks into a corresponding external address, a map comparator in signal communication with the map memory for selectively enabling a memory bank in accordance with its external address, a refresh address generator in signal communication with the map comparator for selectively refreshing the enabled memory bank in accordance with its external address, and a refresh counter in signal communication with the refresh address generator for signaling a refresh in accordance with the maximum required refresh time of the enabled memory bank; and where the corresponding method includes determining the maximum required refresh period for each of the memory banks, respectively, prioritizing the memory banks in accordance with their respective refresh periods, utilizing the memory banks in order of their respective prioritizations, selectively disabling at least one of the memory banks in reverse-order of their respective prioritizations, and refreshing only the remaining non-disabled memory banks.

公开(公告)号：DE10131388A1

公开(公告)日：2003-01-16

申请号：DE10131388

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  LINDOLF JUERGEN

IPC: G11C29/00

Abstract: An integrated dynamic memory includes a memory cell array having memory cells each assigned to one of a plurality of groups. The plurality of groups are divided into defect-free groups having exclusively defect-free memory cells and into defective groups having at least one defective memory cell. The memory further includes a memory configuration table that contains a list of the defect-free groups and an assignment unit that, based upon the entries in the memory configuration table, executes memory accesses only to those memory cells assigned to a defect-free group. The total capacity of the memory module, then, is not fixed once and for all with fabrication, but, rather, results only after a memory test, or may even vary in the course of the module lifetime.

公开(公告)号：DE10106486A1

公开(公告)日：2002-08-29

申请号：DE10106486

申请日：2001-02-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  CHRISSOSTOMIDIS IOANNIS

IPC: H03K3/011 ,  H03K3/0231 ,  H03K3/0232 ,  H03K3/57

Abstract: The invention creates an oscillator circuit, in particular for a refresh timer device of a dynamic semiconductor memory, having a capacitor device (C; C') which is connected between a first node (6) and a first supply potential (P2); a current mirror circuit (T1; T2) for supplying a charging current for the capacitor device (C; C') which is connected via a first transistor device (T4) to the first node (6) and which has a current source (SQ) for supplying a substantially temperature-independent reference current (Iref); a second transistor device (T5), which is connected between the first node (6) and the first supply potential (P2); the first and second transistor devices (T4; T5) and a control signal being configured in such a way that the capacitor device (C; C') can be charged via the first node (6) when a potential (Vcomp) at the first node (6) is lower than the reference potential (Vref), and can be discharged via the first node (6) when the potential (Vcomp) at the first node (6) is higher than the reference potential (Vref) such that the signal at an output (A) oscillates.

公开(公告)号：DE10059740C1

公开(公告)日：2002-03-07

申请号：DE10059740

申请日：2000-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI

IPC: H03K19/003

Abstract: The method provides parallel amplification of 2 input signals for providing 2 amplified output signals, with alternation of the amplitudes of the input signals within a given time frame, for providing a first output signal which has a relatively large gradient over a first time frame and a lesser gradient over a second time frame and a second output signal which has a relatively small gradient over a first time frame and a greater gradient over a second time frame. An Independent claim for a circuit with 2 driver stages for parallel read-out of signals is also included.

公开(公告)号：DE10030443A1

公开(公告)日：2002-01-17

申请号：DE10030443

申请日：2000-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  LINDOLF JUERGEN ,  BRASS ECKHARD ,  KLEHN BERND

IPC: H01L21/306 ,  H01L23/367 ,  H01L23/36

Abstract: Production of a heat deviating surface of a component (1) comprises inserting trenches (3) into the component using an etching process. Preferred Features: The surface of the component is covered with a masking layer (2) in prescribed regions and during etching trenches are etched into the non-covered regions of the surface of the component. An etching solution comprising a 25 vol.% tetramethylammonium hydroxide solution or ethylene diamine or hydrazine is used at 70 deg C. The masking layer is applied to regions of the surface of the component in which the component is divided during the subsequent process steps.

公开(公告)号：DE10001371A1

公开(公告)日：2001-08-02

申请号：DE10001371

申请日：2000-01-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  FISCHER HELMUT ,  KUHNE SEBASTIAN

IPC: G11C11/409 ,  G11C11/407 ,  H03F3/45 ,  H03K19/0944 ,  H03F3/347

Abstract: An integrated circuit has a differential amplifier in a basic circuit having two input transistors, a load element and a power source. The power source has an N-type channel MOS transistor whose controlled path is connected to the input transistors and to a supply terminal of the power source. A control terminal of the transistor is connected to a potential that is positive with respect to a reference potential. The supply terminal of the power source is connected to a potential which is negative with respect to the reference potential and which is made available by a voltage source for switching off cell field transistors of a DRAM memory. The gate-source voltage that is increased in this way improves the behavior of the circuit with respect to fluctuations in potential and permits more favorable dimensioning of the transistor.