公开(公告)号：DE102004002464B4

公开(公告)日：2005-12-08

申请号：DE102004002464

申请日：2004-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BUERKE AXEL ,  HAHN JENS ,  SCHMIDBAUER SVEN ,  WEBER DETLEF ,  KLIPP ANDREAS ,  URBANSKY NORBERT

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/283

公开(公告)号：DE102005061821A1

公开(公告)日：2007-06-14

申请号：DE102005061821

申请日：2005-12-23

Applicant: INFINEON TECHNOLOGIES AG ,  NANYA TECHNOLOGY COOPERATION K

Inventor： LO JAMES ,  BUERKE AXEL ,  SCHMIDBAUER SVEN ,  LIN CHIANG-HUNG

IPC: H01L21/283 ,  H01L21/60

Abstract: A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a semiconductor layer, a first layer and a second layer, whereby at least a part of the semi-conductor layer is covered with the first layer, whereby at least a part of the first layer is covered with the second layer, whereby the second layer is exposed to a plasma gas, whereby an upper face of the first layer adjacent to the second layer is treated by the plasma gas and an interlayer is generated between the first and the second layer reducing the thickness of the first layer.

公开(公告)号：DE102004004864A1

公开(公告)日：2005-08-18

申请号：DE102004004864

申请日：2004-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAHN JENS ,  SCHMIDBAUER SVEN ,  BUERKE AXEL

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/336 ,  H01L29/78

Abstract: Gate structure (1) of transistor in semiconductor substrate (10) is formed by structuring layered gate electrode stack (1). On gate dielectric film (9) is deposited polysilicon layer(s) and metal nitride barrier layer (7) is applied and coated with gate metal layer (8). Between polysilicon layer and barrier layer is located metal contact film (6) preventing interaction between nitrogen in barrier layer and silicon in polysilicon layer. Barrier layer is chemically, thermally and mechanically stable layer on contact film. Independent claims are included for gate structure of transistor.

公开(公告)号：DE102004002464A1

公开(公告)日：2005-08-18

申请号：DE102004002464

申请日：2004-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BUERKE AXEL ,  HAHN JENS ,  SCHMIDBAUER SVEN ,  WEBER DETLEF ,  KLIPP ANDREAS ,  URBANSKY NORBERT

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/283

Abstract: Filling contact holes (2) in a dielectric layer (3) on a substrate, with a metal compound, comprises removing impurities from the walls of the holes, gassing out residues at high temperature, and then applying an adhesive layer (4) onto the dielectric surface. The filling (1) is applied to the adhesive layer, so the hole is completely filled The adhesive layer comprises TiN or Ti/TiN.

公开(公告)号：DE10255835A1

公开(公告)日：2004-06-17

申请号：DE10255835

申请日：2002-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BUERKE AXEL ,  BEWERSDORFF-SARLETTE ULRIKE

IPC: H01L21/336 ,  H01L21/768 ,  H01L23/485 ,  H01L29/49 ,  H01L23/532 ,  H01L21/283 ,  H01L29/78

Abstract: A microelectronic component comprises at least a tungsten nitride barrier layer (6) of formula WNx, where x = 0.3 to 0.5. Preferably, there is a tungsten layer on the barrier layer and the device is a field effect transistor. An Independent claim is also included for a production process for the above.

公开(公告)号：DE10032792A1

公开(公告)日：2002-01-17

申请号：DE10032792

申请日：2000-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BUERKE AXEL ,  SCHMIDBAUER SVEN ,  HAHN JENS

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/532

Abstract: Production of a wiring comprises forming contact holes in an insulating layer (2) to form a first wiring layer (1); cleaning one surface of the contact holes; forming a barrier layer (4) on the surface of the contact holes; forming an AlGeCu-containing second wiring layer (5) on the surface of the insulating layer using a low pressure PVD process to fill the holes; forming and structuring a mask layer (7); and structuring the second wiring layer using the mask layer in an anisotropic etching process. Preferred Features: The second wiring layer is formed by depositing a AlGeCu layer at substrate temperatures of more than 100 degrees C. The cleaning step is carried out using a wet chemical process and/or a plasma etching process. An antireflection layer made of titanium nitride is formed on the surface of the second wiring layer.