公开(公告)号：DE102004043626A1

公开(公告)日：2005-11-24

申请号：DE102004043626

申请日：2004-09-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  WEBER ANDREAS ,  KLIPP ANDREAS ,  WELLHAUSEN UWE ,  SPERLICH HANS-PETER

IPC: H01L21/762

Abstract: A production process for a semiconductor structure comprises preparing a silicon semiconductor substrate (1) with a trench (2), filling the trench with spin-on-glass (4) there being an oxide layer (6) between substrate and spin-on-glass and performing a thermal curing step to cure and densify the spin-on-glass.

公开(公告)号：DE102004020328A1

公开(公告)日：2005-11-03

申请号：DE102004020328

申请日：2004-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLIPP ANDREAS

IPC: C09D183/04 ,  C23C16/40 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768

Abstract: Separating a carbon doped silicon containing dielectric layer by low temperature gas phase separation of a surface comprises reacting a silicon organic compound with hydrogen peroxide to separate a dielectric layer on the surface, where the silicon organic compound exhibits at least one Si-O-Si bond. An independent claim is also included for a premetal dielectric (PMD)-semiconductor structure comprising: (a) semiconductor layer, which exhibits a distance between one another on a surface of a layer; and (b) dielectric layer, which exhibits at least a space filled without a cavity.

公开(公告)号：DE10314574B4

公开(公告)日：2007-06-28

申请号：DE10314574

申请日：2003-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOTHES KERSTIN ,  KLIPP ANDREAS ,  SCHMITT FLORIAN ,  HOLLATZ MARK

IPC: H01L21/762

Abstract: Production of a shallow trench insulation structure comprises forming a mask (3) on a substrate (1), forming trenches (2) in the substrate using a mask, selectively depositing a first insulating material (5) to partially fill the trenches with the insulating material in the presence of the mask, and applying a second insulating material (6) on the whole surface of the structure to fill the trenches in the substrate up to the upper side of the mask.

公开(公告)号：DE102005002675A1

公开(公告)日：2006-09-21

申请号：DE102005002675

申请日：2005-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WELLHAUSEN UWE ,  HOLLATZ MARK ,  DAS ARABINDA ,  KLIPP ANDREAS ,  SPERLICH HANS-PETER ,  BIRNER ALBERT ,  HEIDEMEYER HENRY

IPC: H01L21/314 ,  H01L21/762

Abstract: The method involves pretreating a semiconductor structure before superimposing the spin-on layer to obtain a plane surface of the spin-on layer. A liner layer is superimposed on a semiconductor structure before the superimposition of the spin-on-layer. The semiconductor structure supports a planar superimposition of the spin-on layer on it. An oxide layer is superimposed as a liner layer, whose thickness is greater than 2.0 mm. An independent claim is also included for a semiconductor structure, in particular a semiconductor wafer with a substrate.

公开(公告)号：DE102004002464B4

公开(公告)日：2005-12-08

申请号：DE102004002464

申请日：2004-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BUERKE AXEL ,  HAHN JENS ,  SCHMIDBAUER SVEN ,  WEBER DETLEF ,  KLIPP ANDREAS ,  URBANSKY NORBERT

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/283

公开(公告)号：DE102004020834A1

公开(公告)日：2005-11-17

申请号：DE102004020834

申请日：2004-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STAVREV MOMTCHIL ,  WEGE STEPHAN ,  KLIPP ANDREAS ,  HAUPT MORITZ ,  SPERLICH HANS-PETER

IPC: H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242

Abstract: The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate ( 1 ); providing and patterning a silicon nitride layer ( 3 ) on the semiconductor substrate ( 1 ) as topmost layer of a trench etching mask; forming a trench ( 5 ) in a first etching step by means of the trench etching mask; conformally depositing a liner layer ( 10 ) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench ( 5 ); carrying out a V plasma etching step for forming a V profile of the line layer ( 10 ) in the trench ( 5 ); wherein the liner layer ( 10 ) is pulled back to below the top side of the silicon nitride layer ( 3 ); an etching gas mixture comprises C 5 F 8 , O 2 and an inert gas is used in the V plasma etching step; the ratio (V) of C 5 F 8 /O 2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

公开(公告)号：DE10314574A1

公开(公告)日：2004-10-28

申请号：DE10314574

申请日：2003-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOTHES KERSTIN ,  KLIPP ANDREAS ,  SCHMITT FLORIAN ,  HOLLATZ MARK

IPC: H01L21/762

Abstract: Production of a shallow trench insulation structure comprises forming a mask (3) on a substrate (1), forming trenches (2) in the substrate using a mask, selectively depositing a first insulating material (5) to partially fill the trenches with the insulating material in the presence of the mask, and applying a second insulating material (6) on the whole surface of the structure to fill the trenches in the substrate up to the upper side of the mask.

公开(公告)号：DE10250364A1

公开(公告)日：2004-05-19

申请号：DE10250364

申请日：2002-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLIPP ANDREAS ,  SPERLICH HANS-PETER

IPC: H01L21/314 ,  H01L21/768

Abstract: Irregularities and intermediate spaces (4) are filled by a flow-fill process using a filler (9) of low dielectric constant (k). An Independent claim is included for the semiconductor element obtained.

公开(公告)号：DE10249649A1

公开(公告)日：2004-05-13

申请号：DE10249649

申请日：2002-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLIPP ANDREAS ,  RADECKER JOERG ,  SPERLICH HANS-PETER

IPC: H01L21/316 ,  H01L21/762 ,  H01L21/314 ,  H01L21/3105

Abstract: Production of a shallow trench isolation (4) comprises filling a recess (2) in a substrate (1) with a filler (5). The recess has an aspect ratio of more than 5: 1 (5.0) and is partially filled using a flow-fill process followed by plasma treatment.

公开(公告)号：DE102004002464A1

公开(公告)日：2005-08-18

申请号：DE102004002464

申请日：2004-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BUERKE AXEL ,  HAHN JENS ,  SCHMIDBAUER SVEN ,  WEBER DETLEF ,  KLIPP ANDREAS ,  URBANSKY NORBERT

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/283

Abstract: Filling contact holes (2) in a dielectric layer (3) on a substrate, with a metal compound, comprises removing impurities from the walls of the holes, gassing out residues at high temperature, and then applying an adhesive layer (4) onto the dielectric surface. The filling (1) is applied to the adhesive layer, so the hole is completely filled The adhesive layer comprises TiN or Ti/TiN.