公开(公告)号：DE59712661D1

公开(公告)日：2006-07-06

申请号：DE59712661

申请日：1997-03-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIELACHER FRANZ ,  CALDERA PETER ,  HAUPTMANN JOERG ,  KAHL ALEXANDER

IPC: H04B3/20 ,  H04B3/23 ,  H04B7/015

Abstract: The circuit contains a balance filter (6a,6d) controlled by transmission signals (2a,2d); its output signals are combined with a received signal (1a,1d) using a subtraction device (8,10). An impedance matching filter (5) is controlled by the received signal (1a); its output signal is combined with the transmission signal (2d) using an adder (9). An analogue-to-digital converter or ADC (3) converts analogue received signals (1a) into digital form. A digital-to-analogue converter or DAC converts digital transmission signals to analogue form (1d). The impedance matching filter processes digital signals and the balance filter processes analog signals.

公开(公告)号：DE102004027367A1

公开(公告)日：2005-12-29

申请号：DE102004027367

申请日：2004-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CALDERA PETER ,  FERIANZ THOMAS

IPC: G11C7/10 ,  H02H9/02 ,  H02H9/04 ,  H03G11/04 ,  H03G11/08 ,  H04B3/02 ,  H04L12/66 ,  H04M3/00

公开(公告)号：DE10153740A1

公开(公告)日：2003-05-28

申请号：DE10153740

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CALDERA PETER ,  ZOJER HERBERT

IPC: H03H17/02 ,  H04L5/06 ,  H04M11/06

公开(公告)号：DE102004027367B4

公开(公告)日：2011-04-07

申请号：DE102004027367

申请日：2004-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CALDERA PETER ,  FERIANZ THOMAS

IPC: H04B3/02 ,  G11C7/10 ,  H02H9/02 ,  H02H9/04 ,  H03G11/04 ,  H03G11/08 ,  H04L12/66 ,  H04M3/00

公开(公告)号：DE10153740B4

公开(公告)日：2006-05-24

申请号：DE10153740

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CALDERA PETER ,  ZOJER HERBERT

IPC: H04M11/06 ,  H03H17/02 ,  H04L5/06