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公开(公告)号：DE10224977A1
公开(公告)日：2004-01-08
申请号：DE10224977
申请日：2002-06-05
Applicant: INFINEON TECHNOLOGIES AG
Inventor： CHENNUPATI SIVA RAGHURAM
IPC: H03K19/017 , H03G1/00
Abstract: The circuit arrangement (20) has an input terminal to which the signal to be amplified is applied. The circuit also includes a first in first out memory (21) connected to the input terminal to convey the signal to be amplified to a control unit (22). The control unit determines the value of at least two successive signal states within the signal to be amplified. A driver stage (23) has its input connected to the control unit and the memory and its output connected to an output terminal. The driver amplification is controlled in dependence on at least one signal from the control unit.
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公开(公告)号：DE60308637T2
公开(公告)日：2007-08-09
申请号：DE60308637
申请日：2003-03-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KUZMENKA MAKSIM , CHENNUPATI SIVA RAGHURAM , BACHA ABDALLAH , MUFF SIMON
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公开(公告)号：DE10247758A1
公开(公告)日：2003-05-15
申请号：DE10247758
申请日：2002-10-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： CHENNUPATI SIVA RAGHURAM
Abstract: An arithmetic unit (116) processes signal levels (S1,S2) at terminals (112,114) of a bridge (110), to generate an input signal that corresponds to an output signal sent from an integrated circuit (IC) chip (150) through an interface port (104), according to specific formula. The interface port is coupled to a transmission line (180) having specific impedance. Independent claims are also included for the following: (1) memory chip; and (2) data processing system.
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公开(公告)号：DE60308637D1
公开(公告)日：2006-11-09
申请号：DE60308637
申请日：2003-03-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KUZMENKA MAKSIM , CHENNUPATI SIVA RAGHURAM , BACHA ABDALLAH , MUFF SIMON
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