Patent search ap:("INFINEON TECHNOLOGIES AG") AND inv:"DIMITROVA MILENA" Page 1

1.

发明专利
Conductive-bridging random access memory-memory device e.g. programmable metallization cell memory device, has writing potential units providing writing potential, and logic applying writing potential on memory unit in writing mode 未知

公开(公告)号：DE102005061996A1

公开(公告)日：2007-06-28

申请号：DE102005061996

申请日：2005-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ , DIMITROVA MILENA , LIAW CORVIN , ANGERBAUER MICHAEL

IPC: G11C16/12

Abstract: The device has a resistance memory cell (2) with a resistance memory unit (3), and an operating voltage connection for reception of high and low operating potentials. An addressing logic (10) is operated with an operating voltage. Writing potential units (13, 14) provide writing potential, where the potential is higher than the high operating potential or equal or lower than the low operating potential. The logic is formed to apply the writing potential on the resistance memory unit in a writing mode. The logic controls word and bit lines. An independent claim is also included for a method of characterizing a resistance memory cell in a conductive bridging random access memory (CBRAM).

2.

发明专利
Method for producing reference voltage in resistive memory, involves interconnecting two bit line, which has different voltages 未知

公开(公告)号：DE102006013194B3

公开(公告)日：2007-07-05

申请号：DE102006013194

申请日：2006-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LIAW CORVIN , HOENIGSCHMID HEINZ , DIMITROVA MILENA , ANGERBAUER MICHAEL

IPC: G11C7/12 , G11C16/02

Abstract: The method involves interconnecting bit lines (BLt,BLc), which has different voltages. The resistive memory is a resistive semiconductor-memory. Independent claims are included for the following: (1) method to read out memory cell in a resistive memory cell-array in a memory (2) circuit arrangement.

3.

发明专利
未知

公开(公告)号：DE102005061995B4

公开(公告)日：2007-11-08

申请号：DE102005061995

申请日：2005-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ , DIMITROVA MILENA , LIAW CORVIN , ANGERBAUER MICHAEL

IPC: G11C13/02

4.

发明专利
未知

公开(公告)号：DE102006008492B4

公开(公告)日：2008-09-11

申请号：DE102006008492

申请日：2006-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LIAW CORVIN , HOENIGSCHMID HEINZ , DIMITROVA MILENA , ANGERBAUER MICHAEL

IPC: G11C13/02 , G11C7/12

5.

发明专利
Memory data reading method for e.g. conductive bridging RAM memory circuit, involves detecting current flowing via cell and adjusting control parameter based on current, where measuring parameter is selected from different values of cell 未知

公开(公告)号：DE102006033915B3

公开(公告)日：2007-12-13

申请号：DE102006033915

申请日：2006-07-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ , MUELLER GERHARD , DIMITROVA MILENA , LIAW CORVIN

IPC: G11C17/14 , G11C7/12 , G11C16/26

Abstract: The method involves detecting a current (I) flowing through a memory cell (2). A control parameter (S) is adjusted depending on the detected current such that the current corresponds to reference current. The current flowing through the memory cell is compared with the reference current. A measuring parameter is applied to an evaluation transistor, and is changed until a sign changes a difference between the current and the reference current. The measuring parameter is selected from different resistance values of the memory cell. An independent claim is also included for a memory circuit with a reading unit.

6.

发明专利
Storage circuit, has resistance memory cell with selection transistor and resistance memory element, which is connected with disk potential 未知

公开(公告)号：DE102006008492A1

公开(公告)日：2007-08-30

申请号：DE102006008492

申请日：2006-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LIAW CORVIN , HOENIGSCHMID HEINZ , DIMITROVA MILENA , ANGERBAUER MICHAEL

IPC: G11C13/02 , G11C7/12

Abstract: The storage circuit has a resistance memory cell (10) with a selection transistor (12) and a resistance memory element (11), which is switched into row. The resistance memory element is connected with a disk potential (Vpl). A control circuit is designed to steer the select transistor with the help of an activation signal. A pre-charge circuit (19) is coupled with a knot between the select transistor and the resistance memory element. An independent claim is also included for a method for operation of storage circuits.

7.

发明专利
Memory circuit, has discharge circuit formed to make possible discharge current in or from bit circuit to aid recharging of bit circuit, where recharging of bit circuit is caused by changing resistance of resistance memory unit 未知

公开(公告)号：DE102005061995A1

公开(公告)日：2007-06-28

申请号：DE102005061995

申请日：2005-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ , DIMITROVA MILENA , LIAW CORVIN , ANGERBAUER MICHAEL

IPC: G11C13/02

Abstract: The circuit has a resistance memory unit (14) which is connected with a connection with a disc potential. A bit circuit (12) is connected with another connection of the resistance memory unit, and a programming circuit is formed to change resistance of the resistance memory unit. A discharge circuit (20) is formed to make possible a discharge current in or from the bit circuit to aid recharging of the bit circuit, where the recharging of the bit circuit is caused by changing the resistance of the resistance memory unit. An independent claim is also included for a method for operating a memory circuit.

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