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    CURRENT DRIVE CIRCUIT FOR MRAM
    1.
    发明专利
    CURRENT DRIVE CIRCUIT FOR MRAM 审中-公开

    公开(公告)号：JP2002093144A

    公开(公告)日：2002-03-29

    申请号：JP2001197558

    申请日：2001-06-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  MUELLER GERHARD ,  LOEER THOMAS

    IPC: G11C11/14 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To provide a current driver arrangement capable of supplying a large current at a low voltage when the area needs to be small. SOLUTION: In a current driver arrangement described in the above, this problem can be solved by configuring a driver of an n-type field effect transistor and a current source connected in series therewith. Concretely, a current driver arrangement for an MRAM is provided comprising a memory cell field having a plurality of memory cells (Z) at the crossing position of a word line (WL) and a bit line (BL), and drivers (T1, T2) supplied to each end of the above word line (WL) and the above bit line (BL), and allocated to the above word line (WL) and the above bit line (BL).

    DATA MEMORY HAVING A PLURALITY OF BANKS
    2.
    发明专利
    DATA MEMORY HAVING A PLURALITY OF BANKS 审中-公开

    公开(公告)号：JP2002203390A

    公开(公告)日：2002-07-19

    申请号：JP2001339916

    申请日：2001-11-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOENIGSCHMID HEINZ ,  MUELLER GERHARD

    IPC: G11C11/14 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/00 ,  G11C8/12 ,  G11C11/15 ,  G11C11/401 ,  G11C11/407

    Abstract: PROBLEM TO BE SOLVED: To form a memory in which difference of line length between a com mon data port and column connection points are small and short. SOLUTION: This memory is a data memory having a plurality of banks BK, each bank comprises many memory cells, and matrix state arrangement consisting of rows to which row lines WL are allotted and columns to which column lines BL are allotted is formed. The banks BK are arranged vertically in solid as a stack, ends of the column lines connected to each column driving devices LV, SS are at the edges parallel to the rows of banks, these edges are in a common plane, this plane is extended in the direction of row and is substantially perpendicular to the direction of column. The column driving devices LV, SS of all banks BK are arranged densely in the direction of column, and arranged adjacently to the edge of the stack or near the edge as a block.

    ERROR DETECTION AND CORRECTION METHOD AND APPARATUS IN A MAGNETO-RESISTIVE RANDOM ACCESS MEMORY
    4.
    发明申请
    ERROR DETECTION AND CORRECTION METHOD AND APPARATUS IN A MAGNETO-RESISTIVE RANDOM ACCESS MEMORY 审中-公开
    磁阻随机访问存储器中的错误检测和校正方法和装置

    公开(公告)号：WO2004112048A3

    公开(公告)日：2005-04-07

    申请号：PCT/EP2004006019

    申请日：2004-06-03

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

    Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

    IPC: G06F11/10 ,  G11C7/24 ,  G11C11/406 ,  G11C29/00 ,  G11C11/15

    CPC classification number: G11C7/24 ,  G06F11/106 ,  G11C11/406

    Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

    Abstract translation: 本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。 根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。 此后，读出数据位和ECC校验位，并检测和校正任何错误。 然后基于计数开始数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关ECC校验位，并且最终通过检查，校正和恢复数据位 并将ECC校验位存储到存储区域。

    INTEGRATED MEMORY WITH AN ARRANGEMENT OF NON-VOLATILE MEMORY CELLS AND METHOD FOR THE PRODUCTION AND OPERATION OF AN INTEGRATED MEMORY
    5.
    发明申请
    INTEGRATED MEMORY WITH AN ARRANGEMENT OF NON-VOLATILE MEMORY CELLS AND METHOD FOR THE PRODUCTION AND OPERATION OF AN INTEGRATED MEMORY 审中-公开
    具有非易失性存储器电池及其制造方法和操作集成内存组成的阵列集成的内存

    公开(公告)号：WO0243067A3

    公开(公告)日：2002-12-05

    申请号：PCT/DE0104091

    申请日：2001-10-29

    Applicant: INFINEON TECHNOLOGIES AG ,  MUELLER GERHARD ,  SCHLOESSER TILL

    Inventor： MUELLER GERHARD ,  SCHLOESSER TILL

    IPC: H01L27/105 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/112 ,  G11C11/16

    CPC classification number: H01L27/224 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

    Abstract: An integrated memory with an arrangement of non-volatile ferromagnetic storage based memory cells, comprising high-power memory cells having a magnetoresisitive effect (1) with transistor control, and low-cost memory cells having a magnetoresistive effect (2) with memory elements (60) connected between the word lines (70) and bit lines (50). The memory elements (60) directly connected between a bit and a word line (60) are preferably used in the form of memory cell fields which can be superposed on top of the memory cells (1) with a transistor (9), resulting in a high integration density. Production costs are reduced significantly by producing the memory, which comprises two types of cells and meets all system requirements, in a single module and single operation cycle.

    Abstract translation: 一种集成电路存储器，包括非易失性阵列，建立在铁磁性存储存储器单元包括强大的存储器单元用磁阻效应（1）与晶体管的控制和成本存储单元与字线（70）和位线之间的磁阻效应（2）（50） - 连通的存储元件（60）。 直接连接的位线和字线的存储元件（60）之间在可堆叠一（1），其具有晶体管（9），从而达到一个高的集成密度的存储器单元中的其他存储单元阵列上面被优选使用。 通过使由两种类型的组，从而满足在存储器块和处理结果的所有的系统要求，制造成本显着降低。

    6.
    发明专利
    未知

    公开(公告)号：DE60028392T2

    公开(公告)日：2007-06-06

    申请号：DE60028392

    申请日：2000-09-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MUELLER GERHARD ,  GRUENING ULRIKE

    IPC: G11C11/401 ,  G11C11/409 ,  G11C11/4097

    Abstract: An integrated circuit comprising first and second bitline pairs 410 and 420 is described. The bitline paths of a bitline pair are on different bitline levels. The bitline paths of the first and second bitline pairs which are on different bitline levels are adjacent to each other. The first bitline pair comprises m vertical-horizontal twists 440, where m is a whole number>=1, and the second bitline pair comprises n vertical-horizontal twists 460 and 461, where n is a whole number<> m. The vertical-horizontal twists transform coupling noise into common mode noise.

    8.
    发明专利
    未知

    公开(公告)号：DE102004052611A1

    公开(公告)日：2006-05-04

    申请号：DE102004052611

    申请日：2004-10-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PINNOW CAY-UWE ,  HAPP THOMAS ,  KUND MICHAEL ,  MUELLER GERHARD

    IPC: H01L27/24 ,  H01L21/283

    Abstract: A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

    9.
    发明专利
    未知

    公开(公告)号：DE60104979T2

    公开(公告)日：2005-08-25

    申请号：DE60104979

    申请日：2001-01-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： HANSON R ,  MUELLER GERHARD

    IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  G11C5/06 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094 ,  G11C7/00

    Abstract: A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below VDD. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to receive the first reduced voltage signal on the signal line. The input stage is also coupled to a level shifter stage that is arranged to output a set of level shifter stage control signals responsive to the first reduced voltage signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the first reduced voltage signal. There is further included coupling the output node to the second portion of the signal line. The output node also is coupled to an output stage of the reduced voltage repeater circuit. The output stage is configured to output the second reduced voltage signal on the output node responsive to the set of level shifter stage control signals. A voltage range of the second reduced voltage signal is lower than the voltage range of the set of level shifter stage control signals.

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