公开(公告)号：JP2002118238A

公开(公告)日：2002-04-19

申请号：JP2001217382

申请日：2001-07-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To manufacture an MRAM memory cell which is formed of a slight metal coating plane and has essentially simpler structure as compared with the conventional MRAM memory, by using the metal coating plane. SOLUTION: The uppermost metal coating plane is a second metal coating plane, and a reluctance resistor is stretched to a part between a first metal coating plane and the second metal coating plane. As a result, a first metal coating plane conductor path is connected with a stitch contact of a word line and the reluctance resistor. As a result, double function of a word line stitch and a write line for the reluctance resistor can be realized.

公开(公告)号：JP2002203390A

公开(公告)日：2002-07-19

申请号：JP2001339916

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  MUELLER GERHARD

IPC: G11C11/14 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/00 ,  G11C8/12 ,  G11C11/15 ,  G11C11/401 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To form a memory in which difference of line length between a com mon data port and column connection points are small and short. SOLUTION: This memory is a data memory having a plurality of banks BK, each bank comprises many memory cells, and matrix state arrangement consisting of rows to which row lines WL are allotted and columns to which column lines BL are allotted is formed. The banks BK are arranged vertically in solid as a stack, ends of the column lines connected to each column driving devices LV, SS are at the edges parallel to the rows of banks, these edges are in a common plane, this plane is extended in the direction of row and is substantially perpendicular to the direction of column. The column driving devices LV, SS of all banks BK are arranged densely in the direction of column, and arranged adjacently to the edge of the stack or near the edge as a block.

公开(公告)号：JP2001167577A

公开(公告)日：2001-06-22

申请号：JP2000327457

申请日：2000-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C11/401 ,  G11C11/4063

Abstract: PROBLEM TO BE SOLVED: To provide an integrated memory in which damage by obstruction influence caused by capacitive coupling in a word line intersecting with a bit line is prevented. SOLUTION: At least one second amplifier unit per one word line is provided for the purpose of amplifying a decoder signal driven by a first amplifier unit in a word line, the second amplifier unit is arranged in an internal part of a cell field, further, it is connected to a belonging word line.

公开(公告)号：JP2001167571A

公开(公告)日：2001-06-22

申请号：JP2000327115

申请日：2000-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ

IPC: G11C14/00 ,  G11C11/22

Abstract: PROBLEM TO BE SOLVED: To provide an integrated memory which has its constitution different from a known memory cell and contains a memory cell of a 2-transistor/2- capacitor form. SOLUTION: The electrodes of capacitors C1 and C2 are connected to the different electrode potentials VPL1 and VPL2 respectively.

公开(公告)号：JP2002190199A

公开(公告)日：2002-07-05

申请号：JP2001262310

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ

IPC: G01R31/30 ,  G01R31/28 ,  G11C11/14 ,  G11C11/15 ,  G11C29/06 ,  G11C29/50 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To promote aging without additional expense for the aging. SOLUTION: The circuit layout of the present invention is a circuit layout which promotes the aging in MRAM including a memory cell array. In addition, characteristically, memory cells (Z) having soft magnetic layers (WM) and hard magnetic layers (HM) are arranged at the intersecting point of two control lines (WL and BL) in the memory cell array, a controlling signal can be supplied through each of the first control units (1 and 2), the second control units (T5 and T6) are arranged in parallel to the first control units (1 and 2), and larger electric current can be supplied to the corresponding control line (WL) through either of the second control units than through the first control units (1 and 2).

公开(公告)号：JP2002134708A

公开(公告)日：2002-05-10

申请号：JP2001211245

申请日：2001-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/14 ,  G11C7/18 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To reduce nonconforming action caused by overcoupling among the adjacent lines in a memory matrix, comprising a cell field composed of row lines and column lines in which the memory elements are situated at each point, where the row lines and column lines intersect one another, and the column line and/or row lines of the cell field are placed adjacent to each other. SOLUTION: This memory matrix is constituted, such that the order of row lines or column lines are equal in the edges of the memory matrix counterposed to each other regarding changes in the configurational constitution of the lines. As a result of this, additional circuit cost for executing address decoding, namely an additional circuit cost generated when an address line is not assigned correspondingly or it has a different order from the original order is avoided. For the case of MRAM, the connection constitution of the row lines and column lines in both edges of a cell field becomes advantageous. Furthermore, the cell field or its row lines and/or column line is made symmetrical by a mirror image, regarding changes in their arrangement constitution.

公开(公告)号：JP2000353398A

公开(公告)日：2000-12-19

申请号：JP2000126387

申请日：2000-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG

IPC: G01R31/28 ,  G11C11/22 ,  G11C11/401 ,  G11C11/406 ,  G11C14/00 ,  G11C29/34 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide an integrated memory in which simultaneous write-in of the same logic information is easily performed in plural memory cells. SOLUTION: An integrated memory has bit lines BLi, word lines WLk, and memory cells MC arranged at intersections of plate electrode lines PLi. In a first operation mode, a plate electrode line PLi is left at a plate electrode potential VPL of a fixed period of write-in access. In a second operation mode, the bit line is left at a plate electrode potential, on the other hand, a plate electrode line PLi takes the prescribed potential VF other than the plate electrode potential VPL.

公开(公告)号：JP2001351374A

公开(公告)日：2001-12-21

申请号：JP2001121421

申请日：2001-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ

IPC: G11C11/22

Abstract: PROBLEM TO BE SOLVED: To constitute a circuit so that the ratio of bit line capacitance to the capacitance of a ferroelectric capacitor can be selected over further wider range, in a circuit for reading out a memory cell provided with a ferroelectric capacitor. SOLUTION: This circuit is provided with a bit line BL connected to a memory cell FSPZ and a differential amplifier D. An input side DE1 of a first differential amplifier is connected to the bit line BL, and a reference signal VBSOLL is supplied to a second differential amplifier DE2. The device is also provided with a first driver circuit TR1 provided with a driver input side TRE1 and a first driver output side TRA1. A differential amplifier output side DA is connected to the first driver input side TRE1, and the first driver output side TRA1 is connected to the bit line BL, and a potential of the bit line BL is controlled according to a potential of the reference signal VBSOLL.

公开(公告)号：JP2001273791A

公开(公告)日：2001-10-05

申请号：JP2001029947

申请日：2001-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  HOENIGSCHMID HEINZ ,  LAMMERS STEFAN ,  MANYOKI ZOLTAN

IPC: G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor memory constituted so that a redundant memory cell unit can be tested and the circuit configuration therefor is scarcely complexed inevitably. SOLUTION: This memory is provided with a memory cell MC arranged as a normal unit WL being addressable, a memory cell MC arranged as at least one unit RWL1 to replace the normal unit, an address bus 3 to which an address ADR can be applied, a redundant circuit 1 for selecting a redundant unit RWL1 connected to this address bus 3, and a processing unit 2. The processing unit 2 is connected to a terminal A of the address bus 3 at an input side, and connected to an input side of the redundant circuit 1 at an output side. The redundant unit RWL1 can be tested before programming of restoration information in the redundant circuit 1, moreover, the circuit is not made complex so much.

公开(公告)号：JP2001229667A

公开(公告)日：2001-08-24

申请号：JP2001013090

申请日：2001-01-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To constitute a refresh cycle as advantageously as possible regarding a required energy demand in a semiconductor memory. SOLUTION: In this semiconductor memory, a refresh logic circuit (8) is started in the case of detecting a prescribed minimum deviation at the time of comparing the feature amount of at least one reference memory cell (10) with a reference value (VREF).