公开(公告)号：WO03021655A3

公开(公告)日：2003-04-17

申请号：PCT/EP0209521

申请日：2002-08-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FANG SUNFEI

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/02063 ,  H01L21/31138 ,  H01L21/76814

Abstract: A method for cleaning a semiconductor interconnect structure formed in an organic ILD using an anisotropic organic dielectric etch in combination with a sputter clean process. Organic material displaced from the sidewalls to the bottom of the structure by the sputter clean is removed by the ion enhanced organic etch. Interconnect resistance shift is reduced and reliability of the interconnect structure is improved by removing contaminates at the interface of the via/contact, and by increasing adhesion of the liner or plug to the underlying conductive layer.

Abstract translation: 一种使用各向异性有机电介质蚀刻与溅射清洁工艺组合来清洁在有机ILD中形成的半导体互连结构的方法。 通过溅射清洁从结构的侧壁移动到底部的有机材料通过离子增强的有机蚀刻被去除。 通过去除通孔/接触界面处的污染物，以及增加衬垫或插塞与底层导电层的粘合力，可以降低互连电阻位移并提高互连结构的可靠性。

公开(公告)号：DE102004017411B4

公开(公告)日：2010-01-07

申请号：DE102004017411

申请日：2004-04-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  UNITED MICROELECTRONICS CO

Inventor： COWLEY ANDY ,  FANG SUNFEI ,  WANG YUN-YU ,  CLEVENGER LARRY ,  SIMON ANDREW H ,  GRECO STEPHEN ,  CHANDA KAUSHIK ,  SPOONER TERRY ,  YANG CHIH-CHAO

IPC: H01L21/285 ,  H01L21/768

公开(公告)号：DE102004017411A1

公开(公告)日：2005-03-10

申请号：DE102004017411

申请日：2004-04-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  UNITED MICROELECTRONICS CO

Inventor： COWLEY ANDY ,  FANG SUNFEI ,  WANG YUN-YU ,  CLEVENGER LARRY ,  SIMON ANDREW H ,  GRECO STEPHEN ,  CHANDA KAUSHIK ,  SPOONER TERRY ,  YANG CHIH-CHAO

IPC: H01L21/768 ,  H01L21/285

公开(公告)号：DE102004016700A1

公开(公告)日：2004-11-18

申请号：DE102004016700

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEHAVEN PATRICK W ,  AGNELLO PAUL D ,  WONG KEITH KWONG HON ,  HUANG HSIANG-JEN ,  MURPHY RICHARD J ,  DZIOBKOWSKI CHET ,  CLEVENGER LAWRENCE ,  LAVOIE CHRISTIAN ,  ROVEDO NIVO ,  FANG SUNFEI

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.