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    METHOD OF CLEANING AN INTER-LEVEL DIELECTRIC INTERCONNECT
    4.
    发明申请
    METHOD OF CLEANING AN INTER-LEVEL DIELECTRIC INTERCONNECT 审中-公开
    清洁互连电介质互连的方法

    公开(公告)号：WO03021655A3

    公开(公告)日：2003-04-17

    申请号：PCT/EP0209521

    申请日：2002-08-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FANG SUNFEI

    IPC: H01L21/311 ,  H01L21/768

    CPC classification number: H01L21/02063 ,  H01L21/31138 ,  H01L21/76814

    Abstract: A method for cleaning a semiconductor interconnect structure formed in an organic ILD using an anisotropic organic dielectric etch in combination with a sputter clean process. Organic material displaced from the sidewalls to the bottom of the structure by the sputter clean is removed by the ion enhanced organic etch. Interconnect resistance shift is reduced and reliability of the interconnect structure is improved by removing contaminates at the interface of the via/contact, and by increasing adhesion of the liner or plug to the underlying conductive layer.

    Abstract translation: 一种使用各向异性有机电介质蚀刻与溅射清洁工艺组合来清洁在有机ILD中形成的半导体互连结构的方法。 通过溅射清洁从结构的侧壁移动到底部的有机材料通过离子增强的有机蚀刻被去除。 通过去除通孔/接触界面处的污染物，以及增加衬垫或插塞与底层导电层的粘合力，可以降低互连电阻位移并提高互连结构的可靠性。

    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
    5.
    发明公开
    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
    方法形成自对准DOPPELSALIZID CMOS技术

    公开(公告)号：EP1825508A4

    公开(公告)日：2009-06-24

    申请号：EP05852638

    申请日：2005-12-01

    Applicant: IBM

    Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

    IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

    CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

    METAL GATE MOSFET BY FULL SEMICONDUCTOR METAL ALLOY CONVERSION
    6.
    发明公开
    METAL GATE MOSFET BY FULL SEMICONDUCTOR METAL ALLOY CONVERSION 审中-公开
    METALL-GATE-MOSFET DURCH VOLL-HALBLEITER-METALLEGIERUNGS-KONVERSION

    公开(公告)号：EP1911088A4

    公开(公告)日：2008-11-12

    申请号：EP06789024

    申请日：2006-08-01

    Applicant: IBM

    Inventor： NAYFEH HASAN M ,  KUMAR MAHENDER ,  FANG SUNFEI ,  KEDZIERSKI JAKUB T ,  CABRAL CYRIL JR

    IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L29/00

    CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer (56) that is thick enough to fully convert the semiconductor layer (22) to a semiconductor metal alloy in a first MOSFET type region (40) but only thick enough to partially convert the semiconductor layer (20) to a semiconductor metal alloy in a second MOSFET type region (30). In one embodiment, the gate stack in a first MOSFET region (40) is recessed prior to forming the metal-containing layer (56) so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer (56) is thinned over a first type MOSFET region (40) relative to a second type MOSFET region (30) prior to the conversion process.

    Abstract translation: 描述了MOSFET结构和形成方法。 该方法包括形成厚度足以在第一MOSFET型区域（40）中将半导体层（22）完全转换成半导体金属合金的含金属层（56），但其厚度仅足以部分地将半导体层（ 20）连接到第二MOSFET型区域（30）中的半导体金属合金。 在一个实施例中，在形成含金属层（56）之前使第一MOSFET区域（40）中的栅极堆叠凹陷，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。 在另一个实施例中，在转换过程之前，含金属层（56）在第一类型MOSFET区域（40）上相对于第二类型MOSFET区域（30）变薄。

    Asymmetric semiconductor device, and method of manufacturing the same
    7.
    发明专利
    Asymmetric semiconductor device, and method of manufacturing the same 有权
    非对称半导体器件及其制造方法

    公开(公告)号：JP2010267964A

    公开(公告)日：2010-11-25

    申请号：JP2010109553

    申请日：2010-05-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： YUAN JUN ,  YIN HAIZHOU ,  LIANG YUE ,  YU XIAOJUN ,  FANG SUNFEI ,  CHIDAMBARRAO DURESETI

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

    CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/28132 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/6659 ,  H01L29/7835 ,  Y10S257/90

    Abstract: PROBLEM TO BE SOLVED: To provide an asymmetric semiconductor device, and to provide a method using a spacer scheme in manufacturing the same. SOLUTION: A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high-k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high-k gate dielectric, while, in other embodiments, the first and second conductive spacers are in direct contact with the threshold voltage adjusting material. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种非对称半导体器件，并提供一种使用间隔方案制造该方法的方法。 解决方案：提供了一种半导体结构，其包括位于高k栅极电介质的表面上的不对称栅极堆叠。 非对称栅极堆叠包括第一部分和第二部分，其中第一部分具有与第二部分不同的阈值电压。 不对称栅极堆叠的第一部分包括从底部到顶部的阈值电压调节材料和至少第一导电间隔物，而非对称栅极堆叠的第二部分包括在栅极电介质上的至少第二导电间隔物。 在一些实施例中，第二导电间隔物与下面的高k栅极电介质直接接触，而在其它实施例中，第一和第二导电间隔物与阈值电压调节材料直接接触。 版权所有（C）2011，JPO＆INPIT

    METHOD FOR FORMING SELF-ALIGNED DUAL FULLY SILICIDED GATES IN CMOS DEVICES
    9.
    发明公开
    METHOD FOR FORMING SELF-ALIGNED DUAL FULLY SILICIDED GATES IN CMOS DEVICES 审中-公开
    方法为自对准双VOLLSILIZIERTEN盖茨在CMOS元件训练

    公开(公告)号：EP1831925A4

    公开(公告)日：2009-06-24

    申请号：EP05852637

    申请日：2005-12-01

    Applicant: IBM

    Inventor： FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

    IPC: H01L21/8238

    CPC classification number: H01L21/823835

    Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).

    SELF-FORMING METAL SILICIDE GATE FOR CMOS DEVICES
    10.
    发明公开
    SELF-FORMING METAL SILICIDE GATE FOR CMOS DEVICES 审中-公开
    自FORM金属硅化物-GATE CMOS设备

    公开(公告)号：EP1856725A4

    公开(公告)日：2009-01-14

    申请号：EP06717971

    申请日：2006-01-10

    Applicant: IBM

    Inventor： LUO ZHIJIONG ,  FANG SUNFEI ,  ZHU HUILONG

    IPC: H01L21/336 ,  H01L29/76

    CPC classification number: H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7833

    Abstract: A process for forming a metal silicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (3) (polysilicon or amorphous silicon) is formed overlying the gate dielectric (2); a layer of metal (4) is then formed on the first layer (3), and a second layer of silicon (5) on the metal layer (4). A high-temperature (greater than 700 0C) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer (30) above the gate dielectric (2) by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer (50) from silicon in the second layer (5). The thicknesses of the layers are such that in the high-temperature processing, substantially all the first layer and at least a portion of the second layer are replaced by silicide material. Accordingly, a fully suicided gate structure may be produced.

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