公开(公告)号：JP2004096095A

公开(公告)日：2004-03-25

申请号：JP2003204193

申请日：2003-07-31

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： FUHRMANN DIRK ,  LINDSTEDT REIDAR

IPC: H01L27/108 ,  G11C5/06 ,  G11C7/18 ,  G11C8/14 ,  H01L21/8242 ,  H01L27/02

CPC classification number: H01L27/10876 ,  G11C5/063 ,  G11C7/18 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10885 ,  H01L27/10891

Abstract: PROBLEM TO BE SOLVED: To form control wiring between adjacent first wiring and second wiring without changing lateral intervals between adjacent storage capacitors of a DRAM memory cell.
SOLUTION: Each of second wirings 2 connects memory cells, a storage capacitor 3 of the memory cell is arranged such that a storage capacitor 3 of the memory cell is shifted laterally relative to each second wiring 2. Therefore, the capacitor most proximate to each other is not mutually shifted in the direction of a bit line or a word line but the capacitor is shifted in the oblique direction to the bit line and the word line. Each second wiring 2 is connected to a plurality of memory cells each having the storage capacitor arranged so as to be laterally alternately shifted to the left or right of the second wiring. Thus, while two arrays of memory cells can be controlled by single second wiring, the storage capacitors in the memory cell mutually keep the same space in the same way as a conventional memory cell. Consequently, the required number of the second wirings 2 can be reduced.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2007096268A

公开(公告)日：2007-04-12

申请号：JP2006187619

申请日：2006-07-07

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： FUHRMANN DIRK ,  PERRY ROBERT ,  REHM NORBERT ,  UNG RATH ,  ZIELEMAN JAN

IPC: H01L21/66

CPC classification number: G01R31/31722 ,  G11C29/006 ,  G11C29/028 ,  G11C2029/0407 ,  G11C2029/2602 ,  G11C2029/4402 ,  G11C2029/5602

Abstract: PROBLEM TO BE SOLVED: To provide a method and system which can obtain a method and apparatus setting wafer chips with a single power on and off sequence, and further adjust a chip parameter during a wafer test without utilizing the sequence.
SOLUTION: The method comprises the steps of: assigning a specific identifier to a controllable chip resistor by a program of each wafer chip for test (step 52); storing a value of the parameter fixed by corresponding to each of them inside the chip resistor of the chip selected based on its identifier (step 54); and performing a test evaluating a setting of the parameter for each chip with a desired parameter set simultaneously (step 56).
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种方法和系统，其可以获得具有单个功率开启和关闭序列来设置晶片芯片的方法和装置，并且在晶片测试期间进一步调整芯片参数而不利用该序列。 该方法包括以下步骤：通过用于测试的每个晶片芯片的程序将特定标识符分配给可控芯片电阻器（步骤52）; 根据其标识符将所选择的芯片的片式电阻器中的每一个固定的参数的值存储在其中（步骤54）; 并且执行用同时设定的期望参数来评估每个芯片的参数的设置的测试（步骤56）。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2004042800A3

公开(公告)日：2004-08-05

申请号：PCT/DE0303567

申请日：2003-10-27

Applicant: INFINEON TECHNOLOGIES AG ,  FUHRMANN DIRK ,  LINDSTEDT REIDAR

Inventor： FUHRMANN DIRK ,  LINDSTEDT REIDAR

IPC: H01L21/8242 ,  H01L23/528 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/10885 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10891 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a semiconductor arrangement in which a plurality of individual element fields (2) are arranged along lines (3) of a first type and lines (4) of a second type, on a semiconductor chip (1). The lines of the first or second type extend from an inner region (A;5) to an outer region (B), and the lines of the respective other type of lines extend around the inner region (A;5). A circular central region (5) is formed in one form of embodiment, e.g. in a DRAM memory, said central region containing logic elements which are standard on memory modules. Memory cells (2) are arranged around the central region (5) in such a way that they are located along word lines (3) embodied in the form of concentric rings.

Abstract translation: 它是提供一种半导体器件，其中半导体芯片（1）上的多个Einzellelementefelder的（2）sind.Die沿第一类型的线（3）和管布置（4）的第一或第二类型的第二类型的行是内部部分的 （A; 5）在开始通过导管和所述内部区域围绕相应的另一种导电类型延伸的外区域（B）（A; 5）左右。 在一个实施例中，DRAM存储器，中央部分（5）形成，其具有圆形形状，并且布置在逻辑电路部分的传统的存储装置。 围绕中央Beeich（5）存储单​​元（2）被布置，以使得存储器单元antlang字线以同心环的形式angoerdnet（3）形成。

公开(公告)号：DE102005007084A1

公开(公告)日：2006-08-17

申请号：DE102005007084

申请日：2005-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUHRMANN DIRK ,  SKALITZ MATTHIAS

IPC: G11C7/22 ,  G11C11/4063

Abstract: An integrated semiconductor memory includes a clock generator circuit for generating an internal clock signal that exhibits a certain phase angle with respect to an external clock signal. The phase angle is dependent on a value of the supply voltage of the clock generator circuit. The supply voltage is provided by a controllable voltage generator that includes a controllable resistor. During the production process, the supply voltage generated can be picked up at a contact pad. The value of the controllable resistor is changed in each memory chip by an automatic production machine until the supply voltage generated matches a target value. The controllable voltage generator can be adjusted individually for each memory chip via fuse elements so that the target value of the supply voltage is achieved with high accuracy for each memory chip.

公开(公告)号：DE102004005667B4

公开(公告)日：2006-02-09

申请号：DE102004005667

申请日：2004-02-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LINDSTEDT REIDAR ,  FUHRMANN DIRK

IPC: G11C5/14 ,  G11C7/04 ,  G11C8/08 ,  G11C11/4074 ,  H03B5/30 ,  H03B5/36

Abstract: An integrated semiconductor memory device includes a temperature sensor circuit to generate a temperature-dependent control signal, a reference circuit to generate a temperature-independent reference signal, a comparator circuit and a voltage generator circuit. The comparator circuit generates a first level or second level of an activation signal in a manner dependent on the comparison of the control signal and the reference signal which are both fed to it on an input side. The voltage generator circuit generates a first control signal or a second control signal in a manner dependent on the level of the activation signal. The integrated semiconductor memory enables the generation of two control signals for a selection transistor of a memory cell in a manner dependent on whether the temperature sensor circuit detects a temperature in a first temperature range or in a second temperature range.

公开(公告)号：DE102004005667A1

公开(公告)日：2005-09-15

申请号：DE102004005667

申请日：2004-02-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LINDSTEDT REIDAR ,  FUHRMANN DIRK

IPC: G11C5/14 ,  G11C7/04 ,  G11C8/08 ,  G11C11/4074 ,  H03B5/30 ,  H03B5/36

Abstract: An integrated semiconductor memory device includes a temperature sensor circuit to generate a temperature-dependent control signal, a reference circuit to generate a temperature-independent reference signal, a comparator circuit and a voltage generator circuit. The comparator circuit generates a first level or second level of an activation signal in a manner dependent on the comparison of the control signal and the reference signal which are both fed to it on an input side. The voltage generator circuit generates a first control signal or a second control signal in a manner dependent on the level of the activation signal. The integrated semiconductor memory enables the generation of two control signals for a selection transistor of a memory cell in a manner dependent on whether the temperature sensor circuit detects a temperature in a first temperature range or in a second temperature range.

公开(公告)号：DE10243471A1

公开(公告)日：2004-04-01

申请号：DE10243471

申请日：2002-09-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUHRMANN DIRK ,  BEER PETER

IPC: G11C29/40 ,  G11C29/44 ,  G11C29/00

Abstract: An integrated memory circuit has a memory cell array and a test circuit. The test circuit generates an assessment datum, the assessment datum is dependent on a result of a comparison between a datum read from the memory cell array and a datum previously written to the memory cell array. A coding unit is coupled to the test circuit in order to code a plurality of assessment signals to form a coded test signal, a voltage signal is assigned to the plurality of test data as coded test datum.

公开(公告)号：DE10234945B3

公开(公告)日：2004-01-29

申请号：DE10234945

申请日：2002-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STIEF REIDAR ,  FUHRMANN DIRK

IPC: H01L27/108 ,  G11C5/06 ,  G11C7/18 ,  G11C8/14 ,  H01L21/8242 ,  H01L27/02 ,  G11C5/10

Abstract: A semiconductor memory has a novel geometry of a memory cell array. Without reducing the distance between storage capacitors that are the most closely adjacent to one another it is possible to structure additional lines between adjacent lines in particular word lines. In a preferred embodiment, the number of word lines required for the number of memory cells remaining the same is reduced, as a result of which word line drivers are saved and substrate area is gained.

公开(公告)号：DE10361024A1

公开(公告)日：2005-07-28

申请号：DE10361024

申请日：2003-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LINDSTEDT REIDAR ,  FUHRMANN DIRK

IPC: G11C7/00 ,  G11C29/00 ,  G11C29/34

Abstract: A test process for an integrated semiconductor memory with control, memory cell and select transistor comprises switching from normal to test operation. One signal blocks the select transistors and a second signal makes them conductive. Testing occurs between reading data in and blocking transistors and between blocking and conductive switching. An independent claim is also included for an integrated semiconductor memory as above.

公开(公告)号：AU2003287853A1

公开(公告)日：2004-06-07

申请号：AU2003287853

申请日：2003-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUHRMANN DIRK ,  LINDSTEDT REIDAR

IPC: H01L21/8242 ,  H01L23/528 ,  H01L27/02 ,  H01L27/108 ,  H01L21/00

Abstract: The semiconducting arrangement has several fields of individual elements (2) arranged on lines of first (3) and second (4) types on a semiconducting chip (1). The lines of the first or second type run from an inner region (5) to an outer region and the lines of the other type run around the inner region so as to enclose the inner region. An auxiliary area is arranged in the inner region.