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公开(公告)号：DE10146149B4
公开(公告)日：2004-04-29
申请号：DE10146149
申请日：2001-09-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STIEF REIDAR
Abstract: In a clock-synchronously operated semiconductor memory, particularly a DDR SDRAM, data are read in clock-synchronously with respect to a data strobe signal in the normal mode, according to standard. During the test mode, a DQ receiver is supplied with the operating clock signal instead of the DQS signal. A downstream memory element is bridged by a direct signal path. To change over, multiplexers/demultiplexers driven by the test mode control signal are provided. The data signal supplied to the memory cell array is available immediately after a write command has been applied to the memory cell array.
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公开(公告)号：DE10234945B3
公开(公告)日：2004-01-29
申请号：DE10234945
申请日：2002-07-31
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STIEF REIDAR , FUHRMANN DIRK
IPC: H01L27/108 , G11C5/06 , G11C7/18 , G11C8/14 , H01L21/8242 , H01L27/02 , G11C5/10
Abstract: A semiconductor memory has a novel geometry of a memory cell array. Without reducing the distance between storage capacitors that are the most closely adjacent to one another it is possible to structure additional lines between adjacent lines in particular word lines. In a preferred embodiment, the number of word lines required for the number of memory cells remaining the same is reduced, as a result of which word line drivers are saved and substrate area is gained.
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公开(公告)号：DE10257665B3
公开(公告)日：2004-07-01
申请号：DE10257665
申请日：2002-12-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FUHRMANN DIRK , STIEF REIDAR
IPC: H01L21/8242 , H01L27/02 , H01L27/108 , H01L29/76
Abstract: A semiconductor memory can have first lines to which memory cells are connected and that run divergently with respect to one another, and second lines to which the memory cells are connected that are curved. Combining the geometry of the memory cell array with storage capacitors laterally offset allows signal delays along word lines and bit lines to be aligned regardless of the position of a memory cell in the memory cell array. The geometry of the memory cell array allows short signal propagation times to be attained particularly along the first lines, which are divergent with respect to one another, this simplifying error-free operation of a semiconductor memory particularly at high clock frequencies.
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公开(公告)号：DE10252058A1
公开(公告)日：2004-05-27
申请号：DE10252058
申请日：2002-11-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STIEF REIDAR , FUHRMANN DIRK
IPC: H01L21/8242 , H01L23/528 , H01L27/02 , H01L27/108 , H01L27/10
Abstract: The semiconducting arrangement has several fields of individual elements (2) arranged on lines of first (3) and second (4) types on a semiconducting chip (1). The lines of the first or second type run from an inner region (5) to an outer region and the lines of the other type run around the inner region so as to enclose the inner region. An auxiliary area is arranged in the inner region.
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公开(公告)号：DE10246790A1
公开(公告)日：2004-04-22
申请号：DE10246790
申请日：2002-10-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor： PFEIFFER JOHANN , STIEF REIDAR
Abstract: The device has a memory cell field for storing data and an access controller for controlling read/write access to the cell field that accesses the memory cell field in a first memory operating mode so that a first data item (DL1) to be written in a write cycle is written into the cell field with a write latency and in a second mode so that no latency is used and the data item is written in more rapidly.
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Patent Agency Ranking
公开(公告)号：DE10130363A1
公开(公告)日：2003-01-02
申请号：DE10130363
申请日：2001-06-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BEER PETER , STIEF REIDAR , GRUBER ARNDT , BENZINGER HERBERT
IPC: G11C7/18 , G11C11/408 , G11C11/4097 , G11C11/409
Abstract: An integrated memory circuit includes a memory cell addressed through a first word line and read through a first bit line. The first word line is connected to a word line control circuit for activating, based upon an address, a first word line associated with the memory cell to be read. A data item stored in the addressable memory cell is read through the first bit line using a read apparatus, in particular, a sense amplifier. A second word line is provided to connect a capacitance element to a second bit line, the second bit line being adjacent to the first bit line. The word line control circuit is adapted to connect the capacitance element to the second bit line using the second word line substantially simultaneously with activation of the first word line. A method for reading the data item is also provided.
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公开(公告)号：DE10308926B4
公开(公告)日：2005-02-24
申请号：DE10308926
申请日：2003-02-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STIEF REIDAR
IPC: H01L21/60 , H01L23/485 , H01L25/065 , H01L23/50
Abstract: The semiconductor appliance comprises support element (1), and at least two semiconductor substrates (2,3), each with at least one conductive track (10) coupled to at least one contact region (8) in side face (12) of substrate.Both substrates are so fitted in adjacent, or staked positions that always one main surface(s) of substrate rests on support element, or other substrate, orthogonally to side face. Thus electric contact is made between contact regions of both substrates. There is a possibility to incorporate third semiconductor substrate in specified manner. Independent claims are included for manufacturing method of semiconductor appliance.
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公开(公告)号：DE10120764B4
公开(公告)日：2004-12-23
申请号：DE10120764
申请日：2001-04-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STIEF REIDAR , ROHLEDER MARKUS
Abstract: A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is described. The configuration has a delay locked loop (DLL) circuit for synchronizing an internal clock between a respective circuit and an external clock of the circuit system according to the phase difference between the two clocks in a manner dependent on phase changes in the signals. A response sensitivity of the DLL circuit is defined by a filter, which enables a renewed synchronization only after the arrival of a plurality of phase change events. The filter provided for setting the response sensitivity of the DLL circuit is of a variable configuration.
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公开(公告)号：DE10146149A1
公开(公告)日：2003-04-24
申请号：DE10146149
申请日：2001-09-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STIEF REIDAR
Abstract: In a clock-synchronously operated semiconductor memory, particularly a DDR SDRAM, data are read in clock-synchronously with respect to a data strobe signal in the normal mode, according to standard. During the test mode, a DQ receiver is supplied with the operating clock signal instead of the DQS signal. A downstream memory element is bridged by a direct signal path. To change over, multiplexers/demultiplexers driven by the test mode control signal are provided. The data signal supplied to the memory cell array is available immediately after a write command has been applied to the memory cell array.
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公开(公告)号：DE10129783C1
公开(公告)日：2003-01-02
申请号：DE10129783
申请日：2001-06-20
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STIEF REIDAR
Abstract: The delay locked loop has a delay stage with a variable delay inserted between a clock signal input and a clock signal output, a phase detector (15) receiving the input and output signals of the delay stage and a filter (16) with a multi-stage counter (210), controlled by the phase difference provided by the phase detector, coupled to the delay stage for controlling the delay time. A regulating logic (17) is connected between the output and a further input of the filter, for controlling the number of active counter stages connected between its input and output.
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