公开(公告)号：DE10343388A1

公开(公告)日：2005-02-10

申请号：DE10343388

申请日：2003-09-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BEER PETER ,  OSTENDORF HANS-CHRISTOPH ,  SKALITZ MATTHIAS

IPC: G11C17/18 ,  G11C29/00 ,  G11C29/24

Abstract: The integrated circuit has a fuse memory (1) permanently storing a setting value for the integrated circuit, the latter brought into an output mode via a pre-defined setting value stored in the fuse memory, the setting value entered in the fuse memory after a programming step used for bringing the integrated circuit into an operating mode, with inactive switching of the fuse memory after the programming step by a switching device (8). A test circuit (9) switches the fuse memory into its inactive state upon a test mode, so that the integrated circuit is operated in its output mode with the pre-defined setting value.

公开(公告)号：DE102005007084A1

公开(公告)日：2006-08-17

申请号：DE102005007084

申请日：2005-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUHRMANN DIRK ,  SKALITZ MATTHIAS

IPC: G11C7/22 ,  G11C11/4063

Abstract: An integrated semiconductor memory includes a clock generator circuit for generating an internal clock signal that exhibits a certain phase angle with respect to an external clock signal. The phase angle is dependent on a value of the supply voltage of the clock generator circuit. The supply voltage is provided by a controllable voltage generator that includes a controllable resistor. During the production process, the supply voltage generated can be picked up at a contact pad. The value of the controllable resistor is changed in each memory chip by an automatic production machine until the supply voltage generated matches a target value. The controllable voltage generator can be adjusted individually for each memory chip via fuse elements so that the target value of the supply voltage is achieved with high accuracy for each memory chip.