Abstract:
The invention is based on the finding that the grouping of individually addressable units of a memory (12) into groups or pages (12a) already present in many systems can be used for substantially reducing the complexity of the address-dependent key generation while only insubstantially decreasing security, if a page pre-key is calculated (36) on the basis of a page address (30a) and the individual key is determined on the basis of the page pre-key and the word address (30b). As a result, the address-dependent key generation can be split up into a cryptographically demanding and relatively time-consuming process to be carried out rarely, namely page pre-key generation (34), and a fast step (36) of virtually low technical complexity which has to be carried out for every word or every individually addressable unit (12b), namely determination of the individual key on the basis of the page pre-key and the word address (30b).
Abstract:
A device for generating a pseudo-random sequence of numbers comprises a feedforward device (1) and a feedback device (8) that is connected between an input (6) and an output (7) of the feedforward device (1). The feedback device comprises a variable feedback property (9, 10) and is designed for modifying the feedback property (9, 10) according to a state of one memory device (4) among the number of memory devices of the feedforward device (1). The inventive device can be conveniently implemented with regard to hardware and furnishes pseudo-random sequences with a long period and a high linear complexity.
Abstract:
Decoder 100 zum Auswerten einer ermittelten Ausprägung von physikalischen, unklonbaren Eigenschaften eines physikalischen Objekts 2; 3, wobei der Decoder 100 ein rückgekoppeltes Schieberegister 140 mit mehreren Registerelementen umfasst. Das rückgekoppelte Schieberegister implementiert einen Simplex-Code implementiert und ist konfiguriert, auf der Basis eines in das rückgekoppelte Schieberegister 140 eingespeisten Registervektors 132 ein entsprechendes Syndrom zu bestimmen und in den mehreren Registerelementen zu speichern. Der Decoder umfasst auch eine Kombinationseinrichtung 150, die konfiguriert ist, zumindest eine Untermenge der Registerelemente des rückgekoppelten Schieberegisters 140 algebraisch zu kombinieren und einen resultierenden Kombinationsergebnisvektor 152 bereitzustellen. Der Decoder umfasst weiterhin einen Mehrheitsentscheider 160, der konfiguriert ist, innerhalb des Kombinationsergebnisvektors 152 einen am häufigsten auftretenden Wert zu ermitteln und als Entscheidungsergebnis 162 bereitzustellen. Ferner umfasst der Decoder 100 einen Eingangswähler 120, der konfiguriert ist, einen Eingang des rückgekoppelten Schieberegisters 140 selektiv mit einer Eingangsschnittstellenanordnung 102 oder einem Ausgang des Mehrheitsentscheiders 160 zu verbinden, um in einem ersten Zustand einen von der Eingangsschnittstellenanordnung 102 bereitgestellten Eingangsvektor 112; 512, der der ermittelten Ausprägung der physikalischen, unklonbaren Eigenschaften entspricht, als Registervektor 132 bereitzustellen, und in einem zweiten Zustand einen Entscheidungsvektor, der das Entscheidungsergebnis 162 und weitere Entscheidungsergebnisse umfasst, als Registervektor 132 bereitzustellen.
Abstract:
The device (100) has a processor (101), a peripheral interface (102) and a bus (103) coupled with the processor and the peripheral interface. A bus encoding mechanism (104) is coupled with the bus between the processor and the peripheral interface. The processor outputs digital signals on the bus. The bus encoding mechanism selectively encodes the digital signals output by the processor depending on an encoding signal (105) e.g. start signal and stop signal, assigned to the digital signals. The peripheral interface outputs the selectively encoded signals. The bus is an advanced microcontroller bus architecture (AMBA) bus, an advanced high-performance bus (AHB), an advanced extensible interface (AXI) bus or an advanced peripheral bus (APB). Independent claims are also included for the following: (1) a method for encoding data (2) a computer program comprising a set of instructions for performing a method for encoding data.
Abstract:
A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently influences the PRNG, and in the second mode the TRNG and the PRNG are connected to the output via the combinational logic.
Abstract:
The device has an encryption/decryption unit (20) to encrypt data words and a control bit vector, of a redundancy unit (12), to obtain encrypted data words and control bit vector. The unit (20) decrypts the encrypted words and vector to obtain decrypted data words and control bit vector. The units (12, 20) are placed before a control unit (14) that forms a total bit vector from the decrypted words and vector. The unit (14) creates, by multiplication of a binary control matrix by the total bit vector, a syndrome bit vector used to check the integrity of the total bit vector. Independent claims are also included for the following: (1) a method for protecting the integrity of data (2) a computer program with a program code for the execution of a method for protecting the integrity of data.