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    Circuit for controlling memory matrix word lines makes and maintains low impedance connection from detection of sensed potential changing towards second potential to defined extent
    1.
    发明专利
    Circuit for controlling memory matrix word lines makes and maintains low impedance connection from detection of sensed potential changing towards second potential to defined extent 未知

    公开(公告)号：DE10050770A1

    公开(公告)日：2002-05-02

    申请号：DE10050770

    申请日：2000-10-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  GRAETZ THORALF ,  RUEHLAND KLAUS

    IPC: G11C8/08 ,  G11C7/00 ,  G11C8/00

    Abstract: The circuit has selectively addressable driver stages connected to word lines to form a low impedance connection between a word line end and sources of first or second potentials. Auxiliary stages per word line sense connection point voltages and are activated by enabling signals to make and maintain a low impedance connection from detection that the sensed potential has changed from the first potential towards the second to a defined extent. The circuit has a number of selectively addressable driver stages (20) connected to word lines (WL) and responsive to address and control signals to form a low impedance connection between the relevant word line end and optionally sources of first or second potentials (H,L) with a defined difference. Auxiliary stages (30,40) connected to each word line sense connection point voltages and are activated by enabling signals to make and maintain a low impedance connection from the time at which it is detected that the sensed potential has changed from the first potential towards the second potential to a defined extent.

    2.
    发明专利
    未知

    公开(公告)号：DE19960557B4

    公开(公告)日：2006-09-07

    申请号：DE19960557

    申请日：1999-12-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAETZ THORALF ,  FISCHER HELMUT

    IPC: G11C11/407 ,  G11C11/4076

    Abstract: An integrated dynamic semiconductor memory has memory cells which are provided in a matrix-like memory cell array and are combined to form units with column lines and row lines. The integrated dynamic semiconductor memory has a decoder for selecting one of the column lines and a sense amplifier which is jointly allocated to all the memory cells in a selected column line. The sense amplifier is connected to a data signal line for the purpose of further processing a data signal from an addressed memory cell. The decoder for selecting one of the column lines and the sense amplifier are provided at the edge and on opposite sides of the memory cell array. By separating the control for selection of the column lines and of the data output path, successive steps in the process of read access can be controlled in a self-adjusting manner by the respective preceding signal.

    4.
    发明专利
    未知

    公开(公告)号：DE59809778D1

    公开(公告)日：2003-11-06

    申请号：DE59809778

    申请日：1998-07-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HEYNE PATRICK ,  HAERLE DIETER ,  GRAETZ THORALF

    IPC: G06F3/00 ,  G06F13/42 ,  G11C7/18 ,  H03K19/00 ,  H04L25/02

    Abstract: A data bus comprising of n+1 (n is greater than or equal to 2) conductor lines, which form n true-only lines and lead from input blocks (2,3,4) to n output blocks (5,6,7). One true-only line and the single complement line are assigned to an input block (2) lying at the start of the data bus (1) and having the longest signal transit time, with a NAND-gate (10) connected in series and whose output is connected to each output block (5,6,7). The output blocks each have a tri-state inverter (11) controlled by the check-back signal, the NAND-gate has further delay elements in particular two-series connected inverters, connected to it on the load side.

    5.
    发明专利
    未知

    公开(公告)号：DE59911631D1

    公开(公告)日：2005-03-24

    申请号：DE59911631

    申请日：1999-03-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAETZ THORALF ,  HAERLE DIETER ,  HEYNE PATRICK

    IPC: G11C29/04 ,  G11C29/00 ,  G11C29/02

    Abstract: A circuit configuration and a method for automatic recognition and elimination of word line/bit line short circuits in a memory cell configuration containing sensor amplifiers, in which the sensor amplifiers split the memory cell configuration into memory blocks. To this end, a fuse is provided in the bit lines in each memory block upstream of the respective sensor amplifiers, the fuse being blown as a result of an appropriate voltage difference being applied in a test mode.

    6.
    发明专利
    未知

    公开(公告)号：DE59914524D1

    公开(公告)日：2007-11-29

    申请号：DE59914524

    申请日：1999-05-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HEYNE PATRICK ,  GRAETZ THORALF ,  HAERLE DIETER ,  JOHNSON BRET

    IPC: H03K5/151

    Abstract: The signal generator includes a first branch, in which an input signal (IN) is fed from an input connection (5) over a pass element (2) to a first output connection (7). There is a second branch, in parallel to the first branch, in which the input signal is fed via an invertor (1) to a second output connection (6). The first and the second output connections are fed via an equalising arrangement (8) with first and second output nodes (CLKN, CLKP), in which the equalizing arrangement equalises the different time delays of the signals in the first and in the second branch.

    7.
    发明专利
    未知

    公开(公告)号：DE19841446C2

    公开(公告)日：2003-06-18

    申请号：DE19841446

    申请日：1998-09-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAETZ THORALF

    IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C29/00

    Abstract: An electronic circuit configuration having two lines and a detector device which is allocated to the two lines. The circuit configuration detects a potential difference on the lines and controls a change in the line potentials in response to this. Each line is allocated a switch that is driven by the detector device and, after actuation by the detector device, connects the potential of an associated line to a reference-ground potential that is coupled to the switch.

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