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    1.
    发明专利
    未知

    公开(公告)号：DE59914524D1

    公开(公告)日：2007-11-29

    申请号：DE59914524

    申请日：1999-05-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HEYNE PATRICK ,  GRAETZ THORALF ,  HAERLE DIETER ,  JOHNSON BRET

    IPC: H03K5/151

    Abstract: The signal generator includes a first branch, in which an input signal (IN) is fed from an input connection (5) over a pass element (2) to a first output connection (7). There is a second branch, in parallel to the first branch, in which the input signal is fed via an invertor (1) to a second output connection (6). The first and the second output connections are fed via an equalising arrangement (8) with first and second output nodes (CLKN, CLKP), in which the equalizing arrangement equalises the different time delays of the signals in the first and in the second branch.

    3.
    发明专利
    未知

    公开(公告)号：DE59911631D1

    公开(公告)日：2005-03-24

    申请号：DE59911631

    申请日：1999-03-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAETZ THORALF ,  HAERLE DIETER ,  HEYNE PATRICK

    IPC: G11C29/04 ,  G11C29/00 ,  G11C29/02

    Abstract: A circuit configuration and a method for automatic recognition and elimination of word line/bit line short circuits in a memory cell configuration containing sensor amplifiers, in which the sensor amplifiers split the memory cell configuration into memory blocks. To this end, a fuse is provided in the bit lines in each memory block upstream of the respective sensor amplifiers, the fuse being blown as a result of an appropriate voltage difference being applied in a test mode.

    4.
    发明专利
    未知

    公开(公告)号：DE102005003245B4

    公开(公告)日：2008-05-29

    申请号：DE102005003245

    申请日：2005-01-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROTHLEITNER HUBERT ,  MAYER ALEXANDER ,  HAERLE DIETER

    IPC: B60R21/017

    Abstract: The circuit has first and second supply potential connections (12,23) and ignition element connections (13,22), at least one first and second semiconducting switch element (11,21) integrated into first and second first and second semiconducting bodies (10,20) respectively, a temperature detector, a thermally conducting support element and a chip housing (40).

    5.
    发明专利
    未知

    公开(公告)号：DE102005028211B4

    公开(公告)日：2007-02-01

    申请号：DE102005028211

    申请日：2005-06-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BERNARDON DEREK ,  HAERLE DIETER

    IPC: H02H9/04 ,  G05F1/571 ,  H02H3/20 ,  H02H7/20

    Abstract: The arrangement has an n-channel MOSFET with a loading section and a control connection, whose loading section is switched between switching nodes (1, 2). A control circuit (10) is designed for the n-channel MOSFET and detects one of voltages at the switching nodes. The n-channel MOSFET is regulated by a control input, when one of voltages reaches a threshold value. Voltage dividing resistors are attached at one of the switching nodes.

    8.
    发明专利
    未知

    公开(公告)号：DE102009000471A1

    公开(公告)日：2009-08-27

    申请号：DE102009000471

    申请日：2009-01-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BERNARDON DEREK ,  HAERLE DIETER

    IPC: G01R27/02

    Abstract: A circuit and method for capacitor effective series resistance measurement. One embodiment provides a method for measuring the effective series resistance of a capacitor having a capacitor voltage. The method includes amplifying the capacitor voltage with an AC coupled amplifier yielding a first amplified signal. The capacitor is discharged with a constant current for a measurement time thus causing a voltage swing of the capacitor voltage due to a voltage drop across the effective series resistance. The capacitor voltage is amplified with the AC coupled amplifier yielding a second amplified signal being dependent on the voltage swing. The effective series resistance is calculated from the first and the second amplified signals.

    10.
    发明专利
    未知

    公开(公告)号：DE59809778D1

    公开(公告)日：2003-11-06

    申请号：DE59809778

    申请日：1998-07-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HEYNE PATRICK ,  HAERLE DIETER ,  GRAETZ THORALF

    IPC: G06F3/00 ,  G06F13/42 ,  G11C7/18 ,  H03K19/00 ,  H04L25/02

    Abstract: A data bus comprising of n+1 (n is greater than or equal to 2) conductor lines, which form n true-only lines and lead from input blocks (2,3,4) to n output blocks (5,6,7). One true-only line and the single complement line are assigned to an input block (2) lying at the start of the data bus (1) and having the longest signal transit time, with a NAND-gate (10) connected in series and whose output is connected to each output block (5,6,7). The output blocks each have a tri-state inverter (11) controlled by the check-back signal, the NAND-gate has further delay elements in particular two-series connected inverters, connected to it on the load side.

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