公开(公告)号：JP2005109486A

公开(公告)日：2005-04-21

申请号：JP2004280772

申请日：2004-09-28

Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

Inventor： HEDLER HARRY ,  IRSIGLER ROLAND

IPC: H01L25/18 ,  H01L21/60 ,  H01L21/98 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To provide a multichip module in which many of multilayer chips are interconnected with ease and with cost reduction.
SOLUTION: This method comprises: a process of providing at least one contact bump 11 on a substrate 10; a process of applying rewiring elements 12 to the substrate 10 and the contact bump(s) 11, and of patterning for obtaining a contact element 13 (or contact elements 13); a process of providing semiconductor chips 15 on the substrate 10 which has electrical contact connection consisting of the rewiring elements 12; and a process of providing sealing elements 16 which exhibit no electrical conductivity on the semiconductor chips 15, the substrate 10, the rewiring elements 12, and the at lease one contact bump 11 so that one surface 16' makes contact with the contact element(s) 13. The first surface 16' of one sealing element 16 functions as a substrate. The rewiring elements 12 corresponding to the surface 16' are electrically connected to the contact element(s) 13 of the at least one contact bump 11 on the underlying flat surface.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种多芯片模块，其中许多多层芯片易于互连并且降低成本。 解决方案：该方法包括：在衬底10上提供至少一个接触凸块11的工艺; 将重新布线元件12施加到基板10和接触凸块11以及用于获得接触元件13（或接触元件13）的图案化的过程; 在基板10上设置半导体芯片15的工艺，该半导体芯片15具有由重新布线元件12组成的电接触连接; 以及提供在半导体芯片15，基板10，重新布线元件12和至少一个接触凸块11上不具有导电性的密封元件16的过程，使得一个表面16'与接触元件（s）接触 ）13.一个密封元件16的第一表面16'用作基底。 对应于表面16'的重新布线元件12电连接到下面的平坦表面上的至少一个接触凸块11的接触元件13。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2006287235A

公开(公告)日：2006-10-19

申请号：JP2006103004

申请日：2006-04-04

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： MEYER TORSTEN ,  HEDLER HARRY

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05644 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: PROBLEM TO BE SOLVED: To provide a package with which die bonding of laminated die is easy and wire bonding work is easy. SOLUTION: A package of laminated dies 21 and 29 comprises a printed circuit board 20 having a contact region of the upper surface and a landing pad 33 that surrounds the contact region. On the opposite surface of the board, solder balls 36 are arranged. The solder balls 36 are electrically connected to the landing pad 33 by a wire inside the board. The die 21 mounted on the printed circuit board 20 is surrounded by a frame 23 and the second die 29 is mounted thereon. The pad 26 provided on the frame 23 of the die 21 and the pad 32 of the die 29 are electrically connected to the landing pad of the printed circuit board by wire bond. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种容易进行层压模的管芯接合的封装，并且引线接合工作容易。 解决方案：层叠模具21和29的封装包括具有上表面的接触区域的印刷电路板20和围绕接触区域的着陆焊盘33。 在板的相对表面上布置有焊球36。 焊球36通过板内的线电连接到着陆焊盘33。 安装在印刷电路板20上的模具21被框架23包围，并且第二模具29被安装在其上。 设置在管芯21的框架23上的焊盘26和管芯29的焊盘32通过引线接合电连接到印刷电路板的着陆焊盘。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004186688A

公开(公告)日：2004-07-02

申请号：JP2003401482

申请日：2003-12-01

Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

Inventor： HEDLER HARRY ,  IRSIGLER ROLAND ,  MEYER THORSTEN

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L23/3114 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2224/82

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an integrated circuit with a re-wiring element.
SOLUTION: The integrated circuit (23) is formed in a process preparing a carrier element (10) to which demarcated slitting (11) is attached; a process in which the integrated circuit (14) is mounted on the carrier element (10) upside down, and the slitting (11) is located above at least one connecting element (15) of the integrated circuit (14); a process in which an insulated element (17) is mounted on the side which is not covered by the integrated circuit (14) of the carrier element (10), except the connecting element (15) in the slitting (11); a process which attaches the re-interconnect line element (18, 19) which is patterned to the insulated element (17); a process which attaches a solder resist element (20) which is patterned to the re-interconnect line element (18, 19) which is patterned; and a process, in which a solder bowl (22) is attached to the region (21) which is not covered by the solder resist element (20) in patterned form.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2006339631A

公开(公告)日：2006-12-14

申请号：JP2006130246

申请日：2006-05-09

Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

Inventor： BLASZCZAK STEPHAN ,  HEDLER HARRY ,  KNUT KAHLISCH ,  KROEHNERT STEFFEN ,  SOO GIL PARK ,  MARTIN REISS ,  INGOLF RAU ,  BERND SCHEIBE

IPC: H05K3/34 ,  H01L23/12 ,  H05K1/18

CPC classification number: H01L23/3128 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48464 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/10568 ,  H05K2201/10734 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To reduce the stress in an electronic component assembly. SOLUTION: A method of manufacturing an electronic component assembly comprises: a step of providing a substrate having a first side surface, a second side surface with first solder connection pads, and a through hole; a step of attaching a semiconductor chip onto the first side surface; a step of performing a molding process on the substrate and the semiconductor chip so as to obtain a mold package that includes a first mold section covering the semiconductor chip on the first side surface and a second mold section extending through the through hole and protruding relative to the solder connection pads on the second side surface; a step of providing a printed circuit board having a surface with second solder connection pads corresponding to the first solder connection pads; and a step of soldering the mold package to the printed circuit board by means of solder balls placed between the first and second solder connection pads so that the second mold section forms a spacer structure supporting the mold package on the surface of the printed circuit board. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：减少电子部件组件中的应力。 解决方案：一种制造电子部件组件的方法包括：提供具有第一侧表面的基板，具有第一焊接连接焊盘的第二侧表面和通孔的步骤; 将半导体芯片附接到第一侧表面上的步骤; 在基板和半导体芯片上进行模制处理的步骤，以获得包括覆盖第一侧表面上的半导体芯片的第一模具部分和延伸穿过通孔的第二模具部分的模具包装体，并且相对于 第二侧表面上的焊料连接焊盘; 提供具有与第一焊料连接焊盘相对应的具有第二焊料连接焊盘的表面的印刷电路板的步骤; 以及通过放置在第一和第二焊料连接焊盘之间的焊料球将模具封装焊接到印刷电路板的步骤，使得第二模具部分形成支撑印刷电路板表面上的模具封装的间隔结构。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006108705A

公开(公告)日：2006-04-20

申请号：JP2005339301

申请日：2005-11-24

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： HEDLER HARRY ,  HAIMERL ALFRED

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/485

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2224/29099 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an electronic component which is strong against mechanical stress in the region of an electrical contact, and to provide a method for manufacturing such a component. SOLUTION: In the electronic component having an electronic circuit and the electronic contact 1 which are disposed at least on the first surface 2 of the electronic component to bond the electronic circuit. At least one flexible elevation 3 made of an insulating material is arranged on the first surface 2. At least one electrical contact 1 is arranged on the at least one flexible elevation 3, and a line path 8 is disposed on the surface of or inside the flexible elevation 3 between the at least one electrical contact 1 and the electronic circuit. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在电接触区域内抵抗机械应力强的电子部件，并提供制造这种部件的方法。 解决方案：在具有电子电路的电子部件和至少设置在电子部件的第一表面2上以接合电子电路的电子触点1。 至少一个由绝缘材料制成的柔性立面3布置在第一表面2上。至少一个电触头1设置在至少一个柔性凸起3上，并且线路8设置在该表面上 在至少一个电触点1和电子电路之间具有柔性的高度3。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004219421A

公开(公告)日：2004-08-05

申请号：JP2004005180

申请日：2004-01-13

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： DOBRITZ STEPHAN ,  WEITZ PETER ,  HEDLER HARRY

IPC: G01R31/26 ,  G01R1/04 ,  G01R1/073 ,  G01R31/28 ,  G01R31/30 ,  H01L21/66 ,  H01L23/04 ,  H01L23/055 ,  H01R33/76

CPC classification number: G01R1/0483 ,  H01L23/04 ,  H01L23/055 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311

Abstract: PROBLEM TO BE SOLVED: To test individual dies before mounted onto a PCB (printed circuit board), and to conduct a test up to burn-in when possible.
SOLUTION: This carrier for storing the dies divided individually (bare chips) for the test and/or the burn-in, and for connecting electrically them is provided with the first contact parts arranged lattice-likely to correspond to the dies. The present invention provides the carrier capable of bringing the dies divided individually into precisely mechanical and electrical contact to execute the function test and the burn-in by an existing device. The dies sucked to an elastic bulged part by prescribed force generated by an evacuation device are brought into contact with the first contact parts of the carrier provided with the elastic bulged part. Each of the first contact part is provided with the second contact part in its tip. Each of the second contact part is connected electrically to the each first contact part.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO03001588A3

公开(公告)日：2003-03-06

申请号：PCT/EP0205254

申请日：2002-05-13

Applicant: INFINEON TECHNOLOGIES AG ,  HEDLER HARRY ,  IRSIGLER ROLAND ,  VASQUEZ BARBARA

Inventor： HEDLER HARRY ,  IRSIGLER ROLAND ,  VASQUEZ BARBARA

IPC: H01L21/66 ,  H01L23/525 ,  H01L21/768 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L22/22 ,  H01L23/525 ,  H01L23/5258 ,  H01L2924/0002 ,  Y10S438/94 ,  H01L2924/00

Abstract: The invention relates to a method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalise an integrated circuit by means of at least one laser via (15) in a layer at least partially covering the circuit. Said component comprises a rewiring of the contact pads. The inventive method comprises the following steps: each laser via is closed by means of a separate covering layer (16) which is to be applied locally; a rewiring extending between the local covering layers (16) is created; the local covering layers (16) are removed; and the laser-induced correction is carried out by means of the open laser vias.

Abstract translation: 一种用于制造电子元件，特别是一个存储器芯片，经由一个或多个到电路至少部分地覆盖用于校准集成电路激光通孔（15）用激光索引修正引入层，其特征在于，所述部件具有接触垫的再布线的方法，包括 以下步骤：封闭每个激光通孔的单独局部施加外层（16）的装置; 产生所述覆盖层（16）延伸的重新布线之间的局部; 本地覆盖层的去除（16）; 进行打开激光通孔的激光诱导的校正。

公开(公告)号：WO2005034235A3

公开(公告)日：2005-11-24

申请号：PCT/EP2004010893

申请日：2004-09-29

Applicant: INFINEON TECHNOLOGIES AG ,  HEDLER HARRY ,  IRSIGLER ROLAND ,  MEYER THORSTEN

Inventor： HEDLER HARRY ,  IRSIGLER ROLAND ,  MEYER THORSTEN

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L23/3114 ,  H01L23/293 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The invention relates to a semiconductor module comprising a semiconductor device (10) provided with a contact device (11) for establishing an electrical contact with a connection device by means of a wiring device (15), and a carrier device (12, 13, 14) for mechanically coupling the semiconductor device (10) to a connection device, the carrier device (12, 13, 14) being inclined between a first elasticity module on the semiconductor device (10) and a second, higher elasticity module on the connection device. The invention also relates to a method for producing a semiconductor module.

Abstract translation: 本发明提供了与准备的半导体模块：包括用于经由一个再布线装置（15）与终端装置的电接触的接触装置（11）的半导体器件（10）; 和支撑装置（12，13，14），用于所述半导体器件（10）传送到终端装置的机械联接器，其中所述支撑装置（12，13，14）具有在半导体器件上的第一弹性模量（10）和弹性的第二更高的模量之间的梯度 具有连接装置上。 本发明还提供了一种用于制造半导体模块的方法。

公开(公告)号：WO0171799A3

公开(公告)日：2002-04-04

申请号：PCT/DE0100702

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES AG ,  HEDLER HARRY ,  MEYER THORSTEN

Inventor： HEDLER HARRY ,  MEYER THORSTEN

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L24/10 ,  H01L21/563 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13099 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12043 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a semiconductor element, comprising a semiconductor chip which has at least one contact pad on a first main side and a protective layer which does not cover the at least one contact pad. The semiconductor element can be connected to a substrate by means of flip-chip contacting. Bumps are provided on the first main side, said bumps being at least partially connected to the at least one contact pad by printed conductors provided on the protective layer. The raised parts can be produced either with printable materials or by multiple galvanisation of the printed conductor ends lying opposite the contact pads.

Abstract translation: 本发明提出了一种具有一半导体芯片，其具有至少在第一主一个接触垫和所述至少一个接触垫节约保护层，其特征在于，通过倒装芯片接合的半导体器件连接到基板上的半导体装置。 在这种情况下与所述一个接触垫被设置在第一主侧隆起连接至少部分地位于所述保护层的导电迹线，至少。 这些脊可以由可印刷材料或由相对的导体端部反复电镀接触垫来产生。

公开(公告)号：DE102006035865B3

公开(公告)日：2008-03-06

申请号：DE102006035865

申请日：2006-08-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEDLER HARRY ,  IRSIGLER ROLAND ,  LEHMANN VOLKER

IPC: H01L21/288 ,  B05C5/02 ,  H01L21/60 ,  H01L23/13 ,  H01L23/50

Abstract: The method involves immersing a transfer plate (10) in a material bath, in which a material is placed in a fluid condition, where the pressure acts at the bath and another pressure dominates in blind holes (100). A pressure difference is made between the pressures at the bath and in the holes, respectively, such that the holes are partially filled with the fluid material. The transfer plate is extracted from the bath. The transfer plate opposite to the target plate is positioned, where the material is casted out from the holes to contact with the target plate and to place at the target plate. An independent claim is also included for a device for executing a method for placing material.