公开(公告)号：JP2004186688A

公开(公告)日：2004-07-02

申请号：JP2003401482

申请日：2003-12-01

Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

Inventor： HEDLER HARRY ,  IRSIGLER ROLAND ,  MEYER THORSTEN

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L23/3114 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2224/82

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an integrated circuit with a re-wiring element.
SOLUTION: The integrated circuit (23) is formed in a process preparing a carrier element (10) to which demarcated slitting (11) is attached; a process in which the integrated circuit (14) is mounted on the carrier element (10) upside down, and the slitting (11) is located above at least one connecting element (15) of the integrated circuit (14); a process in which an insulated element (17) is mounted on the side which is not covered by the integrated circuit (14) of the carrier element (10), except the connecting element (15) in the slitting (11); a process which attaches the re-interconnect line element (18, 19) which is patterned to the insulated element (17); a process which attaches a solder resist element (20) which is patterned to the re-interconnect line element (18, 19) which is patterned; and a process, in which a solder bowl (22) is attached to the region (21) which is not covered by the solder resist element (20) in patterned form.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2005109486A

公开(公告)日：2005-04-21

申请号：JP2004280772

申请日：2004-09-28

Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

Inventor： HEDLER HARRY ,  IRSIGLER ROLAND

IPC: H01L25/18 ,  H01L21/60 ,  H01L21/98 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To provide a multichip module in which many of multilayer chips are interconnected with ease and with cost reduction.
SOLUTION: This method comprises: a process of providing at least one contact bump 11 on a substrate 10; a process of applying rewiring elements 12 to the substrate 10 and the contact bump(s) 11, and of patterning for obtaining a contact element 13 (or contact elements 13); a process of providing semiconductor chips 15 on the substrate 10 which has electrical contact connection consisting of the rewiring elements 12; and a process of providing sealing elements 16 which exhibit no electrical conductivity on the semiconductor chips 15, the substrate 10, the rewiring elements 12, and the at lease one contact bump 11 so that one surface 16' makes contact with the contact element(s) 13. The first surface 16' of one sealing element 16 functions as a substrate. The rewiring elements 12 corresponding to the surface 16' are electrically connected to the contact element(s) 13 of the at least one contact bump 11 on the underlying flat surface.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种多芯片模块，其中许多多层芯片易于互连并且降低成本。 解决方案：该方法包括：在衬底10上提供至少一个接触凸块11的工艺; 将重新布线元件12施加到基板10和接触凸块11以及用于获得接触元件13（或接触元件13）的图案化的过程; 在基板10上设置半导体芯片15的工艺，该半导体芯片15具有由重新布线元件12组成的电接触连接; 以及提供在半导体芯片15，基板10，重新布线元件12和至少一个接触凸块11上不具有导电性的密封元件16的过程，使得一个表面16'与接触元件（s）接触 ）13.一个密封元件16的第一表面16'用作基底。 对应于表面16'的重新布线元件12电连接到下面的平坦表面上的至少一个接触凸块11的接触元件13。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO03001588A3

公开(公告)日：2003-03-06

申请号：PCT/EP0205254

申请日：2002-05-13

Applicant: INFINEON TECHNOLOGIES AG ,  HEDLER HARRY ,  IRSIGLER ROLAND ,  VASQUEZ BARBARA

Inventor： HEDLER HARRY ,  IRSIGLER ROLAND ,  VASQUEZ BARBARA

IPC: H01L21/66 ,  H01L23/525 ,  H01L21/768 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L22/22 ,  H01L23/525 ,  H01L23/5258 ,  H01L2924/0002 ,  Y10S438/94 ,  H01L2924/00

Abstract: The invention relates to a method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalise an integrated circuit by means of at least one laser via (15) in a layer at least partially covering the circuit. Said component comprises a rewiring of the contact pads. The inventive method comprises the following steps: each laser via is closed by means of a separate covering layer (16) which is to be applied locally; a rewiring extending between the local covering layers (16) is created; the local covering layers (16) are removed; and the laser-induced correction is carried out by means of the open laser vias.

Abstract translation: 一种用于制造电子元件，特别是一个存储器芯片，经由一个或多个到电路至少部分地覆盖用于校准集成电路激光通孔（15）用激光索引修正引入层，其特征在于，所述部件具有接触垫的再布线的方法，包括 以下步骤：封闭每个激光通孔的单独局部施加外层（16）的装置; 产生所述覆盖层（16）延伸的重新布线之间的局部; 本地覆盖层的去除（16）; 进行打开激光通孔的激光诱导的校正。

公开(公告)号：WO2005034235A3

公开(公告)日：2005-11-24

申请号：PCT/EP2004010893

申请日：2004-09-29

Applicant: INFINEON TECHNOLOGIES AG ,  HEDLER HARRY ,  IRSIGLER ROLAND ,  MEYER THORSTEN

Inventor： HEDLER HARRY ,  IRSIGLER ROLAND ,  MEYER THORSTEN

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L23/3114 ,  H01L23/293 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The invention relates to a semiconductor module comprising a semiconductor device (10) provided with a contact device (11) for establishing an electrical contact with a connection device by means of a wiring device (15), and a carrier device (12, 13, 14) for mechanically coupling the semiconductor device (10) to a connection device, the carrier device (12, 13, 14) being inclined between a first elasticity module on the semiconductor device (10) and a second, higher elasticity module on the connection device. The invention also relates to a method for producing a semiconductor module.

Abstract translation: 本发明提供了与准备的半导体模块：包括用于经由一个再布线装置（15）与终端装置的电接触的接触装置（11）的半导体器件（10）; 和支撑装置（12，13，14），用于所述半导体器件（10）传送到终端装置的机械联接器，其中所述支撑装置（12，13，14）具有在半导体器件上的第一弹性模量（10）和弹性的第二更高的模量之间的梯度 具有连接装置上。 本发明还提供了一种用于制造半导体模块的方法。

公开(公告)号：DE102006035865B3

公开(公告)日：2008-03-06

申请号：DE102006035865

申请日：2006-08-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEDLER HARRY ,  IRSIGLER ROLAND ,  LEHMANN VOLKER

IPC: H01L21/288 ,  B05C5/02 ,  H01L21/60 ,  H01L23/13 ,  H01L23/50

Abstract: The method involves immersing a transfer plate (10) in a material bath, in which a material is placed in a fluid condition, where the pressure acts at the bath and another pressure dominates in blind holes (100). A pressure difference is made between the pressures at the bath and in the holes, respectively, such that the holes are partially filled with the fluid material. The transfer plate is extracted from the bath. The transfer plate opposite to the target plate is positioned, where the material is casted out from the holes to contact with the target plate and to place at the target plate. An independent claim is also included for a device for executing a method for placing material.

公开(公告)号：DE10202881B4

公开(公告)日：2007-09-20

申请号：DE10202881

申请日：2002-01-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： IRSIGLER ROLAND ,  HEDLER HARRY ,  VASQUEZ BARBARA

IPC: H01L21/78 ,  H01L21/301 ,  H01L21/304 ,  H01L21/44 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00

Abstract: The present invention provides a method of producing semiconductor chips (1a, 1b, 1c; 1a', 1b', 1c') with a protective chip-edge layer (21'', 22''), in particular for wafer level packaging chips, with the steps of: preparing a semiconductor wafer (1); providing trenches (21, 22) in the semiconductor wafer to establish chip edges on a first side of the semiconductor wafer (1); filling the trenches (21, 22) with a protective agent (21'; 22'); grinding back the semiconductor wafer (1) from a second side of the semiconductor wafer (1), which is opposite from the first side, to expose the trenches (21, 22) filled with the protective agent (21'; 22'); and cutting through the trenches (21, 22) filled with the protective agent (21'; 22'), so that the protective chip-edge layer (21'', 22'') comprising the protective agent (21', 22') remains on the chip edges.

公开(公告)号：DE10238816A1

公开(公告)日：2004-03-11

申请号：DE10238816

申请日：2002-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MEYER THORSTEN ,  HEDLER HARRY ,  VASQUEZ BARBARA ,  IRSIGLER ROLAND

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/50

Abstract: Production of connecting regions of an integrated circuit (10) comprises applying a dielectric (12) on the circuit, applying an oxidizable and/or corrodable metallization (13, 14, 15) on the dielectric providing a contact with a contact unit (11) of the circuit, applying a protective unit (16) to prevent oxidation of the metallization underneath, and structuring the protective unit so that it is removed around the connecting regions. An Independent claim is also included for an integrated circuit containing the connecting regions.

公开(公告)号：DE10158307A1

公开(公告)日：2003-02-20

申请号：DE10158307

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANKOWSKY GERD ,  HEDLER HARRY ,  MEYER THORSTEN ,  IRSIGLER ROLAND ,  VASQUEZ BARBARA

IPC: H01L21/56 ,  H01L21/68 ,  H01L21/58 ,  H01L21/60

Abstract: Process for joining switching units arranged on a wafer comprises: applying the wafer on a film; cutting the film to divide the switching units without separating the film; stretching the film; and plugging the chambers between units. Process for joining switching units (101a-101n) arranged on a wafer (100) comprises: applying the wafer on film (102); cutting the film to divide switching units without separating the film; applying on a stretching device (103); stretching the film so that prescribed contacting distance is produced; and plugging the intermediate chambers between the switching units using casting composition (105) to produce modified wafer (101a).

公开(公告)号：DE10345395B4

公开(公告)日：2006-09-14

申请号：DE10345395

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEDLER HARRY ,  MEYER THORSTEN ,  IRSIGLER ROLAND

IPC: H01L23/50 ,  H01L23/14 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H01L27/108

公开(公告)号：DE102004038989A1

公开(公告)日：2005-12-29

申请号：DE102004038989

申请日：2004-08-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOSPODINOVA-DALTCHEVA MINKA ,  THOMAS JOCHEN ,  IRSIGLER ROLAND

IPC: H01L25/065 ,  H01L27/108

Abstract: The module has an inner semiconductor chip stack (2) that exhibits an upper semiconductor chip and a lower semiconductor chip (4). The lower semiconductor chip exhibits a back wiring structure on its back. The lower semiconductor chip is electrically connected with flip chip contacts of the upper semiconductor chip. The back wiring structure stands over bond connections with external contacts of wiring substrates that are connected. An independent claim is also included for a method for manufacturing a semiconductor module.