公开(公告)号：DE10335096A1

公开(公告)日：2004-02-12

申请号：DE10335096

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAKER STEVEN M ,  BERRY II JON S ,  COUSINEAU BRAIN ,  GERSTMEIER GUENTER ,  HEGDE MALATI ,  LEE JINHWAN ,  MALDEI MICHAEL

IPC: H01L21/318 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/148 ,  H01L29/76

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.