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    2.
    发明专利
    未知

    公开(公告)号：DE102004009626A1

    公开(公告)日：2004-11-25

    申请号：DE102004009626

    申请日：2004-02-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BAKER STEVEN M ,  BERRY II JON S ,  COUSINEAU BRAIN ,  GERSTMEIER GUENTER ,  HEDGE MALATI ,  LEE JINHWAN ,  MALDEI MICHAEL ,  ZHANG WENCHAO

    IPC: H01L21/02 ,  H01L27/08 ,  H01L29/94 ,  H01L29/768 ,  H01L21/8234

    Abstract: A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.

    5.
    发明专利
    未知

    公开(公告)号：DE102004023462B4

    公开(公告)日：2006-06-08

    申请号：DE102004023462

    申请日：2004-05-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SOMMER MICHAEL BERNHARD ,  HUBER ANDREAS ,  GERSTMEIER GUENTER

    IPC: H01L23/525 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

    Abstract: A metallization surface ( 5 ), which acts as an etching stop layer during the production of openings ( 4 ) in a passivation layer ( 3 ) applied to its upper face and protects an interconnect structure ( 6 ) arranged underneath it, is arranged in an uppermost metallization level ( 1 ). A further opening is produced in the metal surface ( 5 ), through which a focused ion beam is aimed at the interconnect structure ( 6 ) in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.

    6.
    发明专利
    未知

    公开(公告)号：DE10337050A1

    公开(公告)日：2004-03-04

    申请号：DE10337050

    申请日：2003-08-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GERSTMEIER GUENTER ,  MA DAVID SUITWAI

    IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/082 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    Abstract: A DRAM memory unit contains a memory bit (mbit) transistor and a capacitive region for storing charge. The memory is configured to store data as a charge stored by the capacitive region. Each memory unit is accessed by an associated wordline and the data stored by the memory unit is read from an associated bitline connected to the memory unit. The memory units are connected to the associated wordline via a wordline contact and connected to the associated bitline via a bitline contact. The memory units are arranged in memory unit clusters that include multiple memory units having a common bitline contact. The wordline contact is configured to provide for orientation of the wordlines in the memory array independent of the orientation of the bitlines. The wordline contact is also configured to provide for at least one wordline layer separated from the memory unit by a height of the wordline contact. The wordline contact may be further configured to provide an upper wordline layer and a lower wordline layer each being above the bitline relative to the memory unit.

    7.
    发明专利
    未知

    公开(公告)号：DE10028145A1

    公开(公告)日：2001-12-20

    申请号：DE10028145

    申请日：2000-06-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GERSTMEIER GUENTER ,  ROSSKOPF VALENTIN

    IPC: G11C29/00 ,  H01L23/544 ,  H01L21/66 ,  G01R31/26

    Abstract: The circuit has connection areas and transistors in at least 2 rows. First row transistors are arranged between 2 connecting areas with controled paths connections connected to these areas and all control connections connected to a further connection area. One controled path connection of each second row transistor is connected to a different connecting area, the other to a common second area and their control connections to a common third area. The circuit has a first number of connection areas (P6-P12) for inputting and outputting signals and a second number of transistors (T1-T16,T21-T26) to be tested arranged in at least two rows. Each transistor in the first row is arranged between two connecting areas (P12,P11) with the connections of their controled paths connected to these areas and all their control connections connected to a further connection area (P1). One of the controled path connections of each transistor in a second row is connected to a different connecting area (P11), the other to a common second area (P4) and their control connections to a common third area (P2). Independent claims are also included for the following: a semiconducting wafer with an integrated circuit for testing transistors.

    10.
    发明专利
    未知

    公开(公告)号：DE10028145C2

    公开(公告)日：2002-04-18

    申请号：DE10028145

    申请日：2000-06-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GERSTMEIER GUENTER ,  ROSSKOPF VALENTIN

    IPC: G11C29/00 ,  H01L23/544 ,  H01L21/66 ,  G01R31/26

    Abstract: The circuit has connection areas and transistors in at least 2 rows. First row transistors are arranged between 2 connecting areas with controled paths connections connected to these areas and all control connections connected to a further connection area. One controled path connection of each second row transistor is connected to a different connecting area, the other to a common second area and their control connections to a common third area. The circuit has a first number of connection areas (P6-P12) for inputting and outputting signals and a second number of transistors (T1-T16,T21-T26) to be tested arranged in at least two rows. Each transistor in the first row is arranged between two connecting areas (P12,P11) with the connections of their controled paths connected to these areas and all their control connections connected to a further connection area (P1). One of the controled path connections of each transistor in a second row is connected to a different connecting area (P11), the other to a common second area (P4) and their control connections to a common third area (P2). Independent claims are also included for the following: a semiconducting wafer with an integrated circuit for testing transistors.

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