公开(公告)号：WO0245165A3

公开(公告)日：2002-11-21

申请号：PCT/EP0113900

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES AG ,  KIESLICH ALBRECHT ,  HOEHNSDORF FALKO ,  WEBER DETLEF

Inventor： KIESLICH ALBRECHT ,  HOEHNSDORF FALKO ,  WEBER DETLEF

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L23/5329 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a compact semiconductor structure comprising an insulation layer on a semiconductor substrate and at least two metallic conductor strips (7, 8) in said insulation layer. The invention aims to reduce the capacitive coupling between the neighbouring metallic conductor strips of a semiconductor structure and to enable the production of a more compact semiconductor structure. To achieve this, the inventive semiconductor device is characterised in that the insulation layer comprises a first insulation layer (1) of a predetermined thickness consisting of a first insulation material and a second insulation layer (10) of a predetermined thickness consisting of a second insulation material and located above the first insulation layer (1). The two or more metallic conductor strips (7, 8) extend from the first insulation layer (1) into the second insulation layer (10) and the second insulation material has a lower relative dielectric constant than the first insulation material.

Abstract translation: 本发明涉及一种紧密封装的半导体结构，包括：在半导体衬底上的绝缘体层和至少两层金属导体线路（7,8）的绝缘体层英寸 为了减少半导体结构的相邻金属线之间的电容耦合，从而能够生产致密装填半导体结构的，本发明的半导体装置的特征在于，所述绝缘体层是预定厚度的第一绝缘层（1）（第一绝缘材料和第二绝缘层 10）的第二绝缘体材料的预定厚度的包括，设置（第一绝缘层1），其中所述至少两个金属导体（7,8）延伸（从第一绝缘层10）插入延伸，并且所述第二绝缘体材料上具有相对较低的 具有比所述第一绝缘材料的介电常数。

公开(公告)号：DE10140468B4

公开(公告)日：2006-01-05

申请号：DE10140468

申请日：2001-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOEHNSDORF FALKO

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/768

Abstract: The present invention relates to a process for producing contact holes on a metallization structure, which can be used, for example, to produce electrical contacts between adjacent metallization levels. A dielectric layer is applied to interconnects which are covered with a hard-mask layer that is usually used for patterning the interconnects. Then, contact holes are etched through the dielectric layer, and this step is ended as soon as the hard-mask layer is reached. Then, the hard-mask layer is etched selectively with respect to the dielectric layer, so that the phenomenon where the contact holes break out into the space between adjacent interconnects is minimized. In this way the risk of short circuits is drastically reduced.

公开(公告)号：DE10149736C1

公开(公告)日：2003-04-17

申请号：DE10149736

申请日：2001-10-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOEHNSDORF FALKO ,  BACHMANN JENS ,  BAIER ULLRICH

IPC: H01L21/3213 ,  H01L21/768

Abstract: Etching of metal layer systems comprises providing a semiconductor wafer with at least two aluminum-containing layers consisting of an upper aluminum-containing layer (3) separated from a lower aluminum-containing layer (2) by an intermediate layer (5), and etching of the upper aluminum- containing layer with a first etching angle followed by etching of the lower aluminum- containing layer with a second etching angle different to the first etching angle. A switch is made between the first and the second etching steps as soon as an end point determination identifies that the intermediate layer has been reached. Preferred Features: The first etching step is carried out at a higher etching rate than the second etching step. The etching gas is a mixture of BCl3 and Cl2. During the second etching step the mixture contains a greater quantity of BCl3 and a smaller quantity of Cl2 than the mixture used for the first etching step. The etching gas also contains CH4 and N2. The intermediate layer is a titanium or TiN layer.

公开(公告)号：DE10140468A1

公开(公告)日：2003-03-13

申请号：DE10140468

申请日：2001-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOEHNSDORF FALKO

IPC: H01L21/768

Abstract: The present invention relates to a process for producing contact holes on a metallization structure, which can be used, for example, to produce electrical contacts between adjacent metallization levels. A dielectric layer is applied to interconnects which are covered with a hard-mask layer that is usually used for patterning the interconnects. Then, contact holes are etched through the dielectric layer, and this step is ended as soon as the hard-mask layer is reached. Then, the hard-mask layer is etched selectively with respect to the dielectric layer, so that the phenomenon where the contact holes break out into the space between adjacent interconnects is minimized. In this way the risk of short circuits is drastically reduced.

公开(公告)号：DE10062639A1

公开(公告)日：2002-07-04

申请号：DE10062639

申请日：2000-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOEHNSDORF FALKO ,  KIESLICH ALBRECHT ,  BACHMANN JENS

IPC: H01L21/3213

Abstract: Production of conducting pathways, especially aluminum pathways comprises applying an aluminum conducting layer (13) onto a substrate (11); applying a titanium nitride layer; applying a lacquer mask; structuring the titanium nitride layer to a hard mask (19) using the lacquer mask; and structuring the conducting layer to form the conducting pathways using the hard mask. Preferred Features: The titanium nitride layer is 60-200 nm thick. The aluminum conducting layer contains copper and/or silicon as additives. A titanium layer (12) is applied to the conducting layer before the titanium nitride layer is applied. The conducting pathways have an aspect ratio of more than 2 and have a height of more than 350 nm and a width of less than 180 nm.

公开(公告)号：DE10059935A1

公开(公告)日：2002-06-06

申请号：DE10059935

申请日：2000-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOEHNSDORF FALKO ,  KIESLICH ALBRECHT ,  WEBER DETLEF

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/314 ,  H01L23/58

Abstract: The invention relates to a compact semiconductor structure comprising an insulation layer on a semiconductor substrate and at least two metallic conductor strips (7, 8) in said insulation layer. The invention aims to reduce the capacitive coupling between the neighbouring metallic conductor strips of a semiconductor structure and to enable the production of a more compact semiconductor structure. To achieve this, the inventive semiconductor device is characterised in that the insulation layer comprises a first insulation layer (1) of a predetermined thickness consisting of a first insulation material and a second insulation layer (10) of a predetermined thickness consisting of a second insulation material and located above the first insulation layer (1). The two or more metallic conductor strips (7, 8) extend from the first insulation layer (1) into the second insulation layer (10) and the second insulation material has a lower relative dielectric constant than the first insulation material.