公开(公告)号：JP2002050639A

公开(公告)日：2002-02-15

申请号：JP2001183760

申请日：2001-06-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CURELLO GIUSEPPE ,  KIESLICH ALBRECHT

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a simple and inexpensive method for manufacturing a field effect transistor, having a high switching speed. SOLUTION: An injection step using high energy and a small amount of dose is added, thus providing the method for manufacturing the field effect transistor, where the capacity at a p-n junction part between a source and/or the drain and the substrate is reduced. The reduced capacity at the p-n junction part accelerates the switching sped of the transistor. At that time, the method can be easily integrated into the existing manufacturing method of the field effect transistor.

公开(公告)号：WO03015161A3

公开(公告)日：2003-09-25

申请号：PCT/EP0208484

申请日：2002-07-30

Applicant: INFINEON TECHNOLOGIES AG ,  GRAF WERNER ,  KIESLICH ALBRECHT

Inventor： GRAF WERNER ,  KIESLICH ALBRECHT

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/105

CPC classification number: H01L27/10894 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873

Abstract: The invention relates to a method for integrating field-effect transistors for memory and logic applications in a semiconductor substrate (22). According to said method, the gate dielectric (2) and a semiconductor layer (4) are firstly deposited, on the whole surface thereof, both in the logic and memory areas (6) and (8). The gate electrodes (12) are first of all formed in the memory area (8) from these layers. The source and drain regions (56) are implanted and the memory area (8) is coated with an insulating material (20) in a planarized manner. Only then are the gate electrodes (21) formed in the logic area from the semiconductor layer (4) and the gate dielectric (2).

Abstract translation: 它提出了一种用于集成Feldeffekttransi打扰的用于存储和Logikanwendungenin的半导体衬底（22）的方法，其中首先将Gatedie-lektrikum（2）和（4）中的半导体层两者的逻辑和存储器区域（6）和 （8）被沉积在整个表面上。 对于这些层，首先形成于存储区域（8），所述源和漏区（56）被注入的栅电极（12）和所述存储区域（8）用绝缘材料（20）覆盖的平坦化。 从半导体层（4）和在逻辑区域中的栅极电介质（2）上形成的栅极电极（21）随后仅。

公开(公告)号：WO0245165A3

公开(公告)日：2002-11-21

申请号：PCT/EP0113900

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES AG ,  KIESLICH ALBRECHT ,  HOEHNSDORF FALKO ,  WEBER DETLEF

Inventor： KIESLICH ALBRECHT ,  HOEHNSDORF FALKO ,  WEBER DETLEF

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L23/5329 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a compact semiconductor structure comprising an insulation layer on a semiconductor substrate and at least two metallic conductor strips (7, 8) in said insulation layer. The invention aims to reduce the capacitive coupling between the neighbouring metallic conductor strips of a semiconductor structure and to enable the production of a more compact semiconductor structure. To achieve this, the inventive semiconductor device is characterised in that the insulation layer comprises a first insulation layer (1) of a predetermined thickness consisting of a first insulation material and a second insulation layer (10) of a predetermined thickness consisting of a second insulation material and located above the first insulation layer (1). The two or more metallic conductor strips (7, 8) extend from the first insulation layer (1) into the second insulation layer (10) and the second insulation material has a lower relative dielectric constant than the first insulation material.

Abstract translation: 本发明涉及一种紧密封装的半导体结构，包括：在半导体衬底上的绝缘体层和至少两层金属导体线路（7,8）的绝缘体层英寸 为了减少半导体结构的相邻金属线之间的电容耦合，从而能够生产致密装填半导体结构的，本发明的半导体装置的特征在于，所述绝缘体层是预定厚度的第一绝缘层（1）（第一绝缘材料和第二绝缘层 10）的第二绝缘体材料的预定厚度的包括，设置（第一绝缘层1），其中所述至少两个金属导体（7,8）延伸（从第一绝缘层10）插入延伸，并且所述第二绝缘体材料上具有相对较低的 具有比所述第一绝缘材料的介电常数。

公开(公告)号：DE19944304C2

公开(公告)日：2001-09-20

申请号：DE19944304

申请日：1999-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： UWE MATTHIAS ,  KIESLICH ALBRECHT ,  THIEME PETER ,  VOLAND LARS

IPC: H01L21/3105 ,  H01L23/528 ,  H01L27/108

Abstract: The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact areas. The dielectric layer is composed of a depositable material and covers the metalization layer. The contact areas are formed from many contiguous individual structures, which are so narrow that the depositable material does not form, over the individual structures, any areas which run parallel to the metalization layer. The grid of contiguous individual structures forms a contact area which causes dielectric layer elevations which are particularly low and therefore easy to planarize.

公开(公告)号：DE10142266A1

公开(公告)日：2003-04-03

申请号：DE10142266

申请日：2001-08-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  KIESLICH ALBRECHT ,  SACHSE HERMANN ,  GENZ OLIVER

IPC: H01L21/8242 ,  H01L21/3213 ,  H01L21/8234

Abstract: Process for removing polysilicon (8) applied to a substrate (2) comprises completely removing the polysilicon in first regions (7) of an integrated semiconductor arrangement before the surface of the substrate is reached. A mask (11) is applied to the first regions before the polysilicon is completely removed from the second regions. Preferably an insulating layer, more preferably a gate oxide layer, is used as the substrate. The first regions occupy less space than the second regions. The polysilicon is completely removed by dry etching or wet etching. The first and/or second regions are provided with gate stacks.

公开(公告)号：DE19939852B4

公开(公告)日：2006-01-12

申请号：DE19939852

申请日：1999-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUCH LOTHAR ,  ZELL THOMAS ,  LEHR MATTHIAS UWE ,  KIESLICH ALBRECHT

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are arranged one above the other. The metal islands project laterally beyond the vias to a significant extent on account of the line shortening effect. The vias arranged in layers lying one above the other are laterally offset with respect to one another. The landing pad of the invention is configured as an interconnect running between the vias. On account of the line shortening effect, which is less critical for longer tracks, contact areas provided at the ends of the interconnect do not have to be chosen to be as large as the square contact areas of conventional metal islands and can therefore be accommodated to save more space on a circuit layout to be miniaturized. The shrink factor of such a semiconductor structure is increased.

公开(公告)号：DE10142595A1

公开(公告)日：2003-03-27

申请号：DE10142595

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  KIESLICH ALBRECHT ,  SACHSE HERMANN ,  FELDNER KLAUS

IPC: H01L21/3105 ,  H01L21/762 ,  H01L21/8242

Abstract: A method for planarizing the surface of an isolating layer that is deposited on a semiconductor body is described. Zones where the isolating layer has a low level are covered with a block mask in order to be able to selectively etch zones of the isolating layer with a higher level.

公开(公告)号：DE10062639A1

公开(公告)日：2002-07-04

申请号：DE10062639

申请日：2000-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOEHNSDORF FALKO ,  KIESLICH ALBRECHT ,  BACHMANN JENS

IPC: H01L21/3213

Abstract: Production of conducting pathways, especially aluminum pathways comprises applying an aluminum conducting layer (13) onto a substrate (11); applying a titanium nitride layer; applying a lacquer mask; structuring the titanium nitride layer to a hard mask (19) using the lacquer mask; and structuring the conducting layer to form the conducting pathways using the hard mask. Preferred Features: The titanium nitride layer is 60-200 nm thick. The aluminum conducting layer contains copper and/or silicon as additives. A titanium layer (12) is applied to the conducting layer before the titanium nitride layer is applied. The conducting pathways have an aspect ratio of more than 2 and have a height of more than 350 nm and a width of less than 180 nm.

公开(公告)号：DE10059935A1

公开(公告)日：2002-06-06

申请号：DE10059935

申请日：2000-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOEHNSDORF FALKO ,  KIESLICH ALBRECHT ,  WEBER DETLEF

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/314 ,  H01L23/58

Abstract: The invention relates to a compact semiconductor structure comprising an insulation layer on a semiconductor substrate and at least two metallic conductor strips (7, 8) in said insulation layer. The invention aims to reduce the capacitive coupling between the neighbouring metallic conductor strips of a semiconductor structure and to enable the production of a more compact semiconductor structure. To achieve this, the inventive semiconductor device is characterised in that the insulation layer comprises a first insulation layer (1) of a predetermined thickness consisting of a first insulation material and a second insulation layer (10) of a predetermined thickness consisting of a second insulation material and located above the first insulation layer (1). The two or more metallic conductor strips (7, 8) extend from the first insulation layer (1) into the second insulation layer (10) and the second insulation material has a lower relative dielectric constant than the first insulation material.

公开(公告)号：DE19939597B4

公开(公告)日：2006-07-20

申请号：DE19939597

申请日：1999-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIESLICH ALBRECHT ,  AMON JUERGEN

IPC: H01L21/762

Abstract: A method for fabricating a microelectronic structure includes implanting nitrogen into a semiconductor substrate which is provided with trenches, at least in the region of a main area of the semiconductor substrate. The implantation is intended to be carried out in such a way that a nitrogen concentration at the main area is considerably greater than at the side walls of the trenches. As a result, during subsequent oxidation of the semiconductor substrate, a thinner oxide layer can be formed on the main area, in comparison with the side walls. The oxide layer has a homogeneous transition in the edge region between the main area and the side walls. Implanting nitrogen prior to the oxidation of the semiconductor substrate leads to a uniform oxide layer thickness on the main area.