1.
    发明专利
    未知

    公开(公告)号:DE10327709A1

    公开(公告)日:2005-01-13

    申请号:DE10327709

    申请日:2003-06-21

    Abstract: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.

    2.
    发明专利
    未知

    公开(公告)号:DE10328008B4

    公开(公告)日:2008-04-03

    申请号:DE10328008

    申请日:2003-06-21

    Abstract: An explanation is given of, inter alia, an integrated circuit arrangement ( 100 ) containing an npn transistor ( 102 ) and a pnp transistor ( 104 ). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout ( 142 ) for an edge terminal region ( 120 ) and if the edge terminal region ( 120 ) has a part near the substrate which is arranged in the cutout ( 142 ) and a part remote from the substrate which is arranged outside the cutout ( 142 ) and overlaps the base terminal region ( 139 ).

    3.
    发明专利
    未知

    公开(公告)号:DE10328008A1

    公开(公告)日:2005-02-03

    申请号:DE10328008

    申请日:2003-06-21

    Abstract: An explanation is given of, inter alia, an integrated circuit arrangement ( 100 ) containing an npn transistor ( 102 ) and a pnp transistor ( 104 ). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout ( 142 ) for an edge terminal region ( 120 ) and if the edge terminal region ( 120 ) has a part near the substrate which is arranged in the cutout ( 142 ) and a part remote from the substrate which is arranged outside the cutout ( 142 ) and overlaps the base terminal region ( 139 ).

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