公开(公告)号：WO2005041273A3

公开(公告)日：2005-09-09

申请号：PCT/DE2004002266

申请日：2004-10-12

Applicant: INFINEON TECHNOLOGIES AG ,  HELNEDER JOHANN ,  SCHWERD MARKUS ,  GOEBEL THOMAS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  DREXL STEFAN ,  SECK MARTIN

Inventor： HELNEDER JOHANN ,  SCHWERD MARKUS ,  GOEBEL THOMAS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  DREXL STEFAN ,  SECK MARTIN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a method for reducing parasitic couplings in circuits in which dummy structures are embedded in previous production method steps. The invention aims at providing a method that makes it possible to improve decoupling values and reduce the degree of complexity of said method. This is achieved in that the dummy structures (3) are removed at least partly by means of etching steps and cavities (4) are produced.

Abstract translation: 本发明涉及一种用于减少电路寄生耦合，其中虚设图案被嵌入为以前的制造工艺步骤的目的在于提供通过该解耦值的提高和处理成本降低的方法等。 该目的的实现在于该虚设结构（3）通过蚀刻至少部分地去除和空腔（4）的生成。

公开(公告)号：DE10337569B4

公开(公告)日：2008-12-11

申请号：DE10337569

申请日：2003-08-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HELNEDER JOHANN ,  GOEBEL THOMAS ,  SCHWERD MARKUS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  SECK MARTIN ,  DREXL STEFAN ,  KLEIN WOLFGANG ,  HOMMEL MARTINA

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

公开(公告)号：DE10327709A1

公开(公告)日：2005-01-13

申请号：DE10327709

申请日：2003-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SECK MARTIN ,  BOETTNER THOMAS ,  HUTTNER THOMAS ,  DREXL STEFAN

IPC: H01L21/8228 ,  H01L27/082 ,  H01L21/331

Abstract: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.

公开(公告)号：DE10348641A1

公开(公告)日：2005-05-25

申请号：DE10348641

申请日：2003-10-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HELNEDER JOHANN ,  SCHWERD MARKUS ,  GOEBEL THOMAS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  DREXL STEFAN ,  SECK MARTIN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/76 ,  H01L27/08

公开(公告)号：DE10328008B4

公开(公告)日：2008-04-03

申请号：DE10328008

申请日：2003-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DREXL STEFAN ,  SECK MARTIN ,  BOETTNER THOMAS ,  HUTTNER THOMAS

IPC: H01L27/082 ,  H01L21/8228 ,  H01L29/417

Abstract: An explanation is given of, inter alia, an integrated circuit arrangement ( 100 ) containing an npn transistor ( 102 ) and a pnp transistor ( 104 ). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout ( 142 ) for an edge terminal region ( 120 ) and if the edge terminal region ( 120 ) has a part near the substrate which is arranged in the cutout ( 142 ) and a part remote from the substrate which is arranged outside the cutout ( 142 ) and overlaps the base terminal region ( 139 ).

公开(公告)号：DE10337569A1

公开(公告)日：2005-03-24

申请号：DE10337569

申请日：2003-08-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HELNEDER JOHANN ,  GOEBEL THOMAS ,  SCHWERD MARKUS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  SECK MARTIN ,  DREXL STEFAN ,  KLEIN WOLFGANG ,  HOMMEL MARTINA

IPC: H01L23/485 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

公开(公告)号：DE10328008A1

公开(公告)日：2005-02-03

申请号：DE10328008

申请日：2003-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DREXL STEFAN ,  SECK MARTIN ,  BOETTNER THOMAS ,  HUTTNER THOMAS

IPC: H01L21/8228 ,  H01L27/082 ,  H01L29/417 ,  H01L21/331

Abstract: An explanation is given of, inter alia, an integrated circuit arrangement ( 100 ) containing an npn transistor ( 102 ) and a pnp transistor ( 104 ). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout ( 142 ) for an edge terminal region ( 120 ) and if the edge terminal region ( 120 ) has a part near the substrate which is arranged in the cutout ( 142 ) and a part remote from the substrate which is arranged outside the cutout ( 142 ) and overlaps the base terminal region ( 139 ).