公开(公告)号：JP2005251384A

公开(公告)日：2005-09-15

申请号：JP2005063161

申请日：2005-03-07

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： DEPPE JOACHIM ,  ISLER MARK ,  LUDWIG CHRISTOPH ,  SACHSE JENS-UWE ,  FISCHER JAN-MALTE ,  MIKALO RICARDO PABLO

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/5671 ,  G11C16/0475 ,  G11C16/26

Abstract: PROBLEM TO BE SOLVED: To provide a method for operation of an electrically writable and erasable memory cell where occurrence of an error is avoided properly. SOLUTION: In the method for operation of the memory cell, the memory cell has a channel area (2) in which operation is possible in a first direction and a second direction, and the memory cell is characterized by at least one effective parameter. Information is stored as a difference between a parameter operating in the channel area in the first direction and a parameter operating in the channel area in the second direction. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种电可写和可擦除存储单元的操作方法，其中正确地避免了错误的发生。 解决方案：在存储器单元的操作方法中，存储单元具有通道区域（2），其中可以在第一方向和第二方向上进行操作，并且存储器单元的特征在于至少一个有效的 参数。 信息被存储为在第一方向上在通道区域中操作的参数与在第二方向上在通道区域中操作的参数之间的差异。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：DE102006018234A1

公开(公告)日：2007-10-04

申请号：DE102006018234

申请日：2006-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUDWIG CHRISTOPH ,  ISLER MARK ,  STEIN VON KAMIENSKI ELARD ,  HAGENBECK RAINER

IPC: H01L27/115 ,  H01L21/8247

Abstract: A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semiconductor substrate. The gradient in the lateral direction towards a depletion region of the transistor is larger than the gradient in the vertical direction towards a well region.

公开(公告)号：DE102004056497A1

公开(公告)日：2006-03-30

申请号：DE102004056497

申请日：2004-11-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ISLER MARK ,  SCHLEY JAN-MALTE ,  MIKALO RICARDO ,  DECONINCK PASCAL ,  SACHSE JENS-UWE

IPC: H01L21/762 ,  H01L21/8247 ,  H01L27/115

Abstract: A semiconductor device comprises a transistor body of boron doped semiconductor substrate and a conterminous isolating area formed of insulating material, wherein an oxy-nitride layer is between the transistor body and the isolating area. This invention can be used in a transistor body for example in an NROM cell.

公开(公告)号：DE102005027714A1

公开(公告)日：2006-12-07

申请号：DE102005027714

申请日：2005-06-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLEINT CHRISTOPH ANDREAS ,  SCHLEY JAN-MALTE ,  SCHROER ERWIN ,  SACHSE JENS-UWE ,  WEIN GUENTHER ,  MIKALO RICARDO PABLO ,  ISLER MARK

IPC: H01L27/115 ,  H01L21/8247

Abstract: An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.

公开(公告)号：DE102004010840B4

公开(公告)日：2006-01-05

申请号：DE102004010840

申请日：2004-03-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKALO RICARDO ,  ISLER MARK ,  DEPPE JOACHIM ,  SACHSE JENS-UWE ,  LUDWIG CHRISTOPH ,  FISCHER JAN-MALTE

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: The semi conductor memory cell is of a read write type and has a canal region [2] that operates in a first and second direction. Information is stored based upon the difference in operating voltage in the canal region. The process is not affected by cross coupling between memory cells.

公开(公告)号：DE102005020342A1

公开(公告)日：2006-10-12

申请号：DE102005020342

申请日：2005-05-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEIN GUENTER ,  LUDWIG CHRISTOPH ,  SCHLEY JAN-MALTE ,  SACHSE JENS-UWE ,  DEPPE JOACHIM ,  ISLER MARK ,  KRAUSE MATHIAS ,  MACHILL STEFAN

IPC: H01L21/8247

Abstract: The surfaces of wordline stacks and intermediate areas of a main substrate surface are covered with an oxynitride liner. Either sidewall spacers of BPSG are formed or a further liner of nitride is deposited and spacers of oxide are formed. These spacers are used in a peripheral area of addressing circuitry to implant doped source/drain regions. The oxynitride reduces the stress between the nitride and the semiconductor material and prevents charge carriers from penetrating out of a memory layer of nitride into the liner.

公开(公告)号：DE102004028679A1

公开(公告)日：2006-01-05

申请号：DE102004028679

申请日：2004-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ISLER MARK ,  SACHSE JENS-UWE ,  LUDWIG CHRISTOPH ,  MIKALO RICARDO ,  DECONINCK PASCAL ,  FISCHER JAN-MALTE

IPC: H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L29/00

Abstract: Isolation trench arrangement, which isolates adjacent semiconductor structures ( 1 ), ( 2 ), an isolation trench ( 3 ) being formed in such a way that it penetrates from a substrate surface into the substrate volume ( 0 ) and has at least one insulating substance ( 20 ) and at least one conductive substance ( 21 ), and the conductive substance ( 21 ) is electrically conductively connected to the substrate ( 0 ) via an electrically conductive connection ( 22 ).

公开(公告)号：DE102004010840A1

公开(公告)日：2005-09-29

申请号：DE102004010840

申请日：2004-03-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKALO RICARDO ,  ISLER MARK ,  DEPPE JOACHIM ,  SACHSE JENS-UWE ,  LUDWIG CHRISTOPH ,  FISCHER JAN-MALTE

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: The semi conductor memory cell is of a read write type and has a canal region [2] that operates in a first and second direction. Information is stored based upon the difference in operating voltage in the canal region. The process is not affected by cross coupling between memory cells.