公开(公告)号：DE102005020342A1

公开(公告)日：2006-10-12

申请号：DE102005020342

申请日：2005-05-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEIN GUENTER ,  LUDWIG CHRISTOPH ,  SCHLEY JAN-MALTE ,  SACHSE JENS-UWE ,  DEPPE JOACHIM ,  ISLER MARK ,  KRAUSE MATHIAS ,  MACHILL STEFAN

IPC: H01L21/8247

Abstract: The surfaces of wordline stacks and intermediate areas of a main substrate surface are covered with an oxynitride liner. Either sidewall spacers of BPSG are formed or a further liner of nitride is deposited and spacers of oxide are formed. These spacers are used in a peripheral area of addressing circuitry to implant doped source/drain regions. The oxynitride reduces the stress between the nitride and the semiconductor material and prevents charge carriers from penetrating out of a memory layer of nitride into the liner.

公开(公告)号：DE10324052A1

公开(公告)日：2005-01-05

申请号：DE10324052

申请日：2003-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SACHSE JENS-UWE ,  DEPPE JOACHIM ,  MIKALO RICARDO ,  KRAUSE MATHIAS ,  RICHTER RALF ,  LUDWIG CHRISTOPH ,  KLEINT CHRISTOPH

IPC: H01L21/8246 ,  H01L27/115 ,  H01L21/8247

公开(公告)号：DE10324052B4

公开(公告)日：2007-06-28

申请号：DE10324052

申请日：2003-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SACHSE JENS-UWE ,  DEPPE JOACHIM ,  MIKALO RICARDO ,  KRAUSE MATHIAS ,  RICHTER RALF ,  LUDWIG CHRISTOPH ,  KLEINT CHRISTOPH

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/115

公开(公告)号：DE102004005938A1

公开(公告)日：2005-04-21

申请号：DE102004005938

申请日：2004-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER JAN-MALTE ,  SACHSE JENS-UWE ,  WEIN GUENTER ,  KLEINT CHRISTOPH ,  DEPPE JOACHIM ,  KRAUSE MATHIAS

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

Abstract: The device has a semiconducting body (1) with an active region (2) in semiconducting material between lateral dielectric insulation regions (3), a channel region (4) in the active region, source/drain regions (5) at the ends of the channel region and a gate electrode (6) above it separated from the semiconducting material by a memory layer series (10) containing a memory layer (12) between bounding dielectric layers (11,13). At least one of the bounding layers is thicker towards the lateral edges (7) of the channel region than in a central region of the channel region.

公开(公告)号：DE102005021118A1

公开(公告)日：2006-10-05

申请号：DE102005021118

申请日：2005-05-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DEPPE JOACHIM ,  SACHSE JENS-UWE ,  KLEINT CHRISTOPH ANDREAS ,  LUDWIG CHRISTOPH ,  WEIN GUENTER ,  KRAUSE MATHIAS

IPC: H01L27/115 ,  H01L21/8247

Abstract: A non-volatile semiconductor memory ( 30 ) comprising a semiconductor substrate ( 1 ) and a plurality of memory cells ( 19 ) and methods for manufacturing such a memory is provided. Each memory cell ( 19 ) comprises a charge-trapping element ( 5 ), a gate stack ( 20 ), nitride spacers ( 10 ) and electrically insulating elements ( 21 ). The charge-trapping element ( 5 ) is arranged on the semiconductor substrate ( 1 ) and comprises a nitride layer ( 3 ) sandwiched between a bottom oxide layer ( 2 ) and a top oxide layer ( 4 ), the charge-trapping element ( 5 ) having two lateral sidewalls ( 24 ) opposed to one another. The gate stack ( 20 ) is arranged on top of the charge-trapping element ( 5 ), the gate stack having two lateral sidewalls ( 25 ) opposing one another. The electrically insulating elements ( 21 ) are disposed at opposing sidewalls ( 24 ) of the charge-trapping element ( 5 ) and cover the sidewalls ( 24 ) of the charge-trapping element ( 5 ). The nitride spacers ( 10 ) cover the electrically insulating elements ( 21 ) and are arranged on opposing sidewalls ( 25 ) of the gate stack ( 20 ) and on the electrically insulating elements ( 21 ).