公开(公告)号：WO2004047117A8

公开(公告)日：2004-08-19

申请号：PCT/SG0300264

申请日：2003-11-11

Applicant: INFINEON TECHNOLOGIES AG ,  JOACHIM HANS-OLIVER ,  ROEHR THOMAS ,  WOHLFAHRT JOERG

Inventor： JOACHIM HANS-OLIVER ,  ROEHR THOMAS ,  WOHLFAHRT JOERG

IPC: G11C29/50 ,  G11C29/00 ,  G11C11/22

CPC classification number: G11C29/50 ,  G11C11/22

Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.

Abstract translation: 本发明提供了一种测试模式部分，用于促进用于信号余量的最坏情况产品测试序列，以确保整个组件寿命期间的全部产品功能，从而考虑所有老化效应。 半导体存储器测试模式配置包括用于存储数字数据的第一电容器。 第一电容器通过第一选择晶体管将单元板线连接到第一位线。 第一个选择晶体管通过与字线的连接来激活。 用于存储数字数据的第二电容器通过第二选择晶体管将单元板线连接到第二位线。 第二选择晶体管也通过与字线的连接来激活。 感测放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。 恒定电流移动器，例如恒定电流吸收器或源极，通过第三晶体管连接到第一位线，用于当第三晶体管导通时改变第一位线上的电荷量，以减小差分读取信号。

公开(公告)号：WO2004047115A8

公开(公告)日：2004-08-26

申请号：PCT/SG0300262

申请日：2003-11-11

Applicant: INFINEON TECHNOLOGIES AG ,  JOACHIM HANS-OLIVER ,  JACOB MICHAEL ,  REHM NORBERT

Inventor： JOACHIM HANS-OLIVER ,  JACOB MICHAEL

IPC: G11C29/50 ,  G11C29/00 ,  G11C11/22

CPC classification number: G11C29/50 ,  G11C11/22

Abstract: The present invention provides at test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.

Abstract translation: 本发明在测试模式部分提供了便于针对信号余量的最坏情况产品测试序列，以确保在整个组件寿命期间的全部产品功能，同时考虑到所有的老化效应。 半导体存储器测试模式配置包括用于存储数字数据并通过第一选择晶体管将单元板线连接到第一位线的第一电容器。 通过连接到字线而激活的第一选择晶体管。 第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。 通过与字线的连接激活第二选择晶体管。 读出放大器连接到第一和第二位线，并测量第一和第二位线上的差分读取信号。 第三晶体管在第一和第二位线之间传输电荷，以减少差分读取信号。

公开(公告)号：WO2004047116A8

公开(公告)日：2004-08-26

申请号：PCT/SG0300263

申请日：2003-11-11

Applicant: INFINEON TECHNOLOGIES AG ,  JACOB MICHAEL ,  ROEHR THOMAS ,  WOHLFAHRT JOERG ,  JOACHIM HANS-OLIVER

Inventor： JACOB MICHAEL ,  ROEHR THOMAS ,  WOHLFAHRT JOERG ,  JOACHIM HANS-OLIVER

IPC: G11C29/50 ,  G11C29/00

CPC classification number: G11C29/50 ,  G11C11/22

Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effect into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A potential is connected to the first bit line through a third transistor and changes a pre-charge signal level on the first bit line when the third transistor is turned on to reduce the differential read signal.

Abstract translation: 本发明提供了一种测试模式部分，用于促进信号余量的最坏情况产品测试序列，以确保在整个组件使用寿命期内产生全部产品功能，从而考虑到所有的老化效应。 半导体存储器测试模式配置包括用于存储数字数据的第一电容器。 电容器通过第一选择晶体管将单元板线连接到第一位线。 第一个选择晶体管通过与字线的连接来激活。 第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。 第二选择晶体管也通过与字线的连接来激活。 读出放大器连接到第一和第二位线，并测量第一和第二位线上的差分读取信号。 电位通过第三晶体管连接到第一位线，并且当第三晶体管导通时改变第一位线上的预充电信号电平以减小差分读取信号。

公开(公告)号：WO2004025664A3

公开(公告)日：2004-07-08

申请号：PCT/EP0309775

申请日：2003-09-03

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

Inventor： TAKASHIMA DAISABURO ,  JACOB MICHAEL ,  JOACHIM HANS-OLIVER ,  ROEHR THOMAS ,  WOHLFAHRT JOERG

IPC: G11C29/50 ,  G11C29/00 ,  G11C11/22

CPC classification number: G11C29/50 ,  G11C11/22 ,  G11C2029/1204 ,  G11C2029/5004

Abstract: A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bitlines. During a read access, a selected memory cell produces a differential read signal on the bitlines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.

Abstract translation: 公开了一种用于在存储器访问期间测试差分读取信号的测试电路。 测试电路耦合到一对位线。 在读取访问期间，所选择的存储器单元在位线上产生差分读取信号。 当测试电路被激活时，差分读取信号的幅度是变化的。 这使得能够容易地测试例如存储器IC中的读取信号余量。

公开(公告)号：WO2004029971A3

公开(公告)日：2004-06-03

申请号：PCT/EP0310468

申请日：2003-09-19

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

Inventor： JOACHIM HANS-OLIVER ,  MIYAKAWA TADASHI ,  REHM NORBERT ,  ROEHR THOMAS

IPC: G11C29/00

CPC classification number: G11C29/785 ,  G11C17/14

Abstract: A redundancy unit (204) comprising first (260) and second (270) fuse blocks for programming the redundancy element (220) is disclosed. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before and after packaging.

Abstract translation: 公开了一种包括用于对冗余元件（220）进行编程的第一（260）和第二（270））熔丝块的冗余单元（204）。 一个保险丝盒有激光熔断保险丝和其他电气保险丝。 冗余单元可以通过任一个保险丝块进行编程，使得冗余单元能够用于包装之前和之后识别的缺陷。

公开(公告)号：DE69940761D1

公开(公告)日：2009-06-04

申请号：DE69940761

申请日：1999-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RENGARAJAN RAJESH ,  BEINTNER JOCHEN ,  GRUENING ULRIKE ,  JOACHIM HANS-OLIVER

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/085 ,  H01L27/092 ,  H01L27/108

Abstract: A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.

公开(公告)号：DE60315340D1

公开(公告)日：2007-09-13

申请号：DE60315340

申请日：2003-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOACHIM HANS-OLIVER ,  JACOB MICHAEL

IPC: G11C29/00 ,  G11C11/22 ,  G11C29/50

公开(公告)号：DE10310779B4

公开(公告)日：2007-04-05

申请号：DE10310779

申请日：2003-03-12

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

Inventor： TAKASHIMA DAISABURO ,  SHIRATAKE SHINICHIRO ,  JOACHIM HANS-OLIVER ,  ROEHR THOMAS

IPC: G11C11/22 ,  G11C5/14 ,  G11C7/02 ,  G11C7/22 ,  G11C8/08 ,  G11C16/02 ,  H01L21/8246 ,  H01L27/105

Abstract: A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.

公开(公告)号：AU2003278684A8

公开(公告)日：2004-06-15

申请号：AU2003278684

申请日：2003-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOACHIM HANS-OLIVER ,  JACOB MICHAEL ,  ROEHR THOMAS ,  WOHLFAHRT JOERG

IPC: G11C29/50 ,  G11C29/00

Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data The capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A potential is connected to the first bit line through a third transistor and changes a pre-charge signal level on the first bit line when the third transistor is turned on to reduce the differential read signal.

公开(公告)号：DE60305668D1

公开(公告)日：2006-07-06

申请号：DE60305668

申请日：2003-03-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOACHIM HANS-OLIVER ,  ROEHR THOMAS

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12 ,  G11C11/22

Abstract: Improved sensing of ferroelectric memory cells is disclosed. When a memory access is initiated, the bitlines are precharged to a negative voltage, for example, -0.5 to -1.0V. This increases the effective plateline pulse (V PLH ) to V PLH +the magnitude of the negative voltage. This results in an increase in the difference between V HI and V L0 read signals, thereby increasing the sensing window.