公开(公告)号：DE102004016705A1

公开(公告)日：2004-11-25

申请号：DE102004016705

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： YU CHIENFAN ,  RUPP THOMAS ,  DOBUZINSKI DAVID M ,  DEV PRAKASH C ,  RENGARAJAN RAJESH ,  NAEEM MUNIR-UD-DIN ,  BENEDICT JOHN ,  FALTERMEIER JOHNATHAN E ,  MALDEI MICHAEL

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/283

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

公开(公告)号：DE102004001237A1

公开(公告)日：2005-06-23

申请号：DE102004001237

申请日：2004-01-07

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： LA ROSA GIUSEPPE ,  DELLOW MARK ,  RENGARAJAN RAJESH

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/00 ,  H01L29/78

公开(公告)号：DE69930894T2

公开(公告)日：2006-11-16

申请号：DE69930894

申请日：1999-06-16

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  TOSHIBA KAWASAKI KK

Inventor： RENGARAJAN RAJESH ,  SRINIVASAN RADHIKA ,  INOUE HIROFUMI ,  BEINTNER JOCHEN

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/08

Abstract: A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.

公开(公告)号：DE10310569A1

公开(公告)日：2003-10-02

申请号：DE10310569

申请日：2003-03-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  LEE KIL-HO ,  MANDELMAN JACK A ,  MCSTAY KEVIN ,  RENGARAJAN RAJESH

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/119

Abstract: Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants-an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.

公开(公告)号：DE69940761D1

公开(公告)日：2009-06-04

申请号：DE69940761

申请日：1999-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RENGARAJAN RAJESH ,  BEINTNER JOCHEN ,  GRUENING ULRIKE ,  JOACHIM HANS-OLIVER

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/085 ,  H01L27/092 ,  H01L27/108

Abstract: A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.

公开(公告)号：DE102004016705B4

公开(公告)日：2008-04-17

申请号：DE102004016705

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： YU CHIENFAN ,  RUPP THOMAS ,  DOBUZINSKI DAVID M ,  DEV PRAKASH C ,  RENGARAJAN RAJESH ,  NAEEM MUNIR-UD-DIN ,  BENEDICT JOHN ,  FALTERMEIER JOHNATHAN E ,  MALDEI MICHAEL

IPC: H01L21/283 ,  H01L21/311 ,  H01L21/60 ,  H01L21/8239 ,  H01L21/8242 ,  H01L23/485 ,  H01L29/768

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

公开(公告)号：DE69930894D1

公开(公告)日：2006-05-24

申请号：DE69930894

申请日：1999-06-16

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  TOSHIBA KAWASAKI KK

Inventor： RENGARAJAN RAJESH ,  SRINIVASAN RADHIKA ,  INOUE HIROFUMI ,  BEINTNER JOCHEN

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/08

Abstract: A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.

公开(公告)号：DE10253900A1

公开(公告)日：2003-06-18

申请号：DE10253900

申请日：2002-11-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANG WOO-TAG ,  LEE KIL-HO ,  RENGARAJAN RAJESH

IPC: H01L21/8238 ,  H01L21/336

Abstract: In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate electrode so that there is no boron penetration in the channel region and no boron depletion near the gate oxide, comprising:a) forming a gate oxide layer over a channel of a nMOS site and over a channel of a pMOS site;b) forming an undoped polysilicon layer over the gate oxide layer;c) masking the pMOS site, forming an a-Si layer over the nMOS site using a first heavy ion implantation, and implanting arsenic solely into the a-Si layer;d) masking the nMOS site formed by step c), forming an a-Si layer over the pMOS site using a second heavy ion implantation, and implanting boron solely into the a-Si regions;e) laser annealing the nMOS and pMOS sites for a short time and at an energy level sufficient to melt at least a portion of the a-Si but insufficient to melt the polysilicon; andf) affecting cooling after laser annealing to convert a-Si into polysilicon without gate oxide damage.