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    INTEGRATED MEMORY, AND METHOD FOR GENERATING REFERENCE VOLTAGE ON REFERENCE BIT LINE OF INTEGRATED MEMORY
    3.
    发明专利
    INTEGRATED MEMORY, AND METHOD FOR GENERATING REFERENCE VOLTAGE ON REFERENCE BIT LINE OF INTEGRATED MEMORY 失效

    公开(公告)号：JP2001307478A

    公开(公告)日：2001-11-02

    申请号：JP2001083633

    申请日：2001-03-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  MANYOKI ZOLTAN ,  ESTERL ROBERT ,  ROEHR THOMAS

    IPC: G11C11/22

    Abstract: PROBLEM TO BE SOLVED: To improve accuracy of bit line reference voltage to read and write data in a memory capacitor MC in a memory in which a differential sense amplifier SA is connected to a pair of bit lines, for example, a ferroelectric memory to read and write data in a memory capacitor MC. SOLUTION: A main reference bit line/BL0 is connected to reference voltage VREF through a charging switch element TL. The other reference bit line/BLi is connected to the main bit line/BL0 through a balance adjusting switch element TA for electric charges balance adjustment between parasitic capacitance of each reference bit line. At the time, reference voltage VGEN is separated from the main reference bit line/BL0, other reference bit lines /BL1, /BL2, /BL3 are connected to the main reference bit line in parallel. Thereby, balance adjustment of electric charges accumulated in parasitic capacitance CPi of each reference bit line connected in parallel is performed, reference voltage VREF is distributed as equal plural bit line reference voltage V/BLi.

    MEMORY INTEGRATED CIRCUIT WITH IMPROVED RELIABILITY
    4.
    发明专利
    MEMORY INTEGRATED CIRCUIT WITH IMPROVED RELIABILITY 审中-公开

    公开(公告)号：JP2004005924A

    公开(公告)日：2004-01-08

    申请号：JP2003080601

    申请日：2003-03-24

    Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA CORP

    Inventor： TAKASHIMA DAISABURO ,  SHIRATAKE SHINICHIRO ,  JOACHIM HANS OLIVER ,  ROEHR THOMAS

    IPC: G11C8/08 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105

    Abstract: PROBLEM TO BE SOLVED: To provide a chain structure memory IC with improved reliability by driving a wordline by a mechanism of multi-step voltage, boosting a voltage only when a gate is required and reducing a load to a gate oxidation film. SOLUTION: This invention related to the chain memory IC which drives the wordline by using a mechanism of two-step voltage. During a suspended state, the wordline is maintained by a first logic 1 voltage level. For memory call, a selected wordline is driven by earthing, and on the other hand, a wordline which is not selected is driven by a boosted voltage. The first logic 1 voltage level is lower than the boosted voltage. This reduces the load to the gate oxidation film of a transistor. COPYRIGHT: (C)2004,JPO

    MEMORY DEVICE HAVING PLURAL MEMORY CELLS
    6.
    发明专利
    MEMORY DEVICE HAVING PLURAL MEMORY CELLS 失效

    公开(公告)号：JP2000156091A

    公开(公告)日：2000-06-06

    申请号：JP32163899

    申请日：1999-11-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG

    IPC: G11C14/00 ,  G11C11/22

    Abstract: PROBLEM TO BE SOLVED: To reduce remarkably a time for reading out by connecting respectively one short circuit element to one side bit line of two pairs of bit line, applying a reference signal to a sense amplifier through a first pair of bit line, simultaneously, applying a read-out signal to the sense amplifier through a second pair of bit line. SOLUTION: In a short circuit element SG, being not adjacent bit lines, but every other bit lines are connected mutually. This way is indicated by a bit line BL , BL or bBL , bBL , further, in this case, two control lines INIT , INIT are not used for pre-charge, but used for short-circuiting two bit lines BL , BL or bBL , bBL . Active memory cells L and a reference cell R are arranged comparatively densely in the same block as a memory cell field by arranging utilized pairs of bit line in parallel.

    Semiconductor memory
    7.
    发明专利
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：JP2005339724A

    公开(公告)日：2005-12-08

    申请号：JP2004159758

    申请日：2004-05-28

    Applicant: Infineon Technologies Ag ,  Toshiba Corp ,  インフィネオン テクノロジース アクチエンゲゼルシャフト ,  株式会社東芝

    Inventor： OGIWARA TAKASHI ,  TAKASHIMA DAIZABURO ,  ROEHR THOMAS

    IPC: G11C11/22 ,  G03B42/02 ,  G03C5/16 ,  G11C7/04 ,  G11C7/14

    CPC classification number: G11C7/14 ,  G03B42/02 ,  G11C7/04 ,  G11C11/22

    Abstract: PROBLEM TO BE SOLVED: To generate a reference potential whose temperature dependence and absolute value can be independently controlled.
    SOLUTION: A dummy capacitor driving potential VDC is given to one electrode of a dummy capacitor and a reference potential as a standard for judging a data value of a memory cell is generated on the other electrode. A potential generating circuit generating the driving VDC is constituted of a BGR circuit 11 outputting a VBGR
    TEMP having temperature dependence and resistances R3 and R4 connected in series between an output end of the BGR circuit 11 and a grounding point. The VDC is outputted from the connection point of the resistances R3 and R4. The temperature dependence of the DVC is adjusted by the resistance ratio of resistances R1-1, R1-2 and R2 and the absolute value is adjusted by the resistance ratio of the resistances R3 and R4.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：为了产生可以独立地控制温度依赖性和绝对值的参考电位。 解决方案：在虚拟电容器的一个电极上提供虚拟电容器驱动电位VDC，并且在另一个电极上产生用于判断存储器单元的数据值的标准的参考电位。 产生驱动VDC的电位发生电路由输出具有温度依赖性的VBGR TEMP 的BGR电路11和串联连接在BGR电路11的输出端和接地点 。 VDC从电阻R3和R4的连接点输出。 通过电阻R1-1，R1-2和R2的电阻比来调节DVC的温度依赖性，并且通过电阻R3和R4的电阻比来调节绝对值。 版权所有（C）2006，JPO＆NCIPI

    METHOD FOR OBSTRUCTING UNDESIRABLE PROGRAMMING IN MRAM DEVICE
    8.
    发明专利
    METHOD FOR OBSTRUCTING UNDESIRABLE PROGRAMMING IN MRAM DEVICE 审中-公开

    公开(公告)号：JP2002203388A

    公开(公告)日：2002-07-19

    申请号：JP2001331484

    申请日：2001-10-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FREITAG MARTIN ,  LAMMERS STEFAN ,  GOGL DIETMAR ,  ROEHR THOMAS

    IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To provide a method for obstructing undesirable programming in a MRAM device so that disablement of programming owing to scattered magnetic field of a memory cell being adjacent to a selection memory cell can be surely and simply obstructed. SOLUTION: A current IBL2 flowing in a bit line BL2 generates a scattered magnetic field in a MTJ memory cell I3 in an intersection part of a bit line BL3 and a word line WL1. Then an adequate compensation current IBL3 is made to flow in the bit line BL3 to suppress influence of this scattered magnetic field, scattered magnetic field in the MTJ memory cell I3 can be canceled by compensation magnetic field generated by this compensation current IBL3.

    ELECTRONIC DRIVER CIRCUIT
    9.
    发明专利
    ELECTRONIC DRIVER CIRCUIT 审中-公开

    公开(公告)号：JP2002133855A

    公开(公告)日：2002-05-10

    申请号：JP2001241347

    申请日：2001-08-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  GOGL DIETMAR

    IPC: G11C11/14 ,  G11C8/08 ,  G11C8/10 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To reduce the complexity and occupancy area of wirings in a driver circuit for word lines of a memory matrix. SOLUTION: In the electronic driver circuit for the word lines WL in the memory matrix 3, a driver source 2, for example, coded output sides IV0-IV3 of a current/voltage source are connected to selected word lines WLi-2-WLi+1. In this case, the word lines WL are selected for every block by control signals SLNP, SLN1, SLN2, and the outputs of the driver source 2 are applied to them. In that case, each activated word line WLi is selected by the coding of the driver source 2.

    OPERATION METHOD FOR FERROELECTRIC MEMORY
    10.
    发明专利
    OPERATION METHOD FOR FERROELECTRIC MEMORY 失效

    公开(公告)号：JP2001351375A

    公开(公告)日：2001-12-21

    申请号：JP2001105822

    申请日：2001-04-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HONIGSCHMID HEINZ ,  ROEHR THOMAS

    IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

    Abstract: PROBLEM TO BE SOLVED: To reduce all standby current flowing during standby of a ferroelectric memory. SOLUTION: When a ferroelectric memory having a selection transistor, a memory cell, and a short circuit transistor is operated in a VDD/2 mode, the short circuit transistor is controlled during a standby period after read-out or write-in process controlled through word lines to which memory cells are arranged respectively and bit lines pre-charged in a pre-charge period, electrodes of an accumulation capacitor are short-circuited, a standby period is made temporally same as a pre-charge period, and bit lines have an another potential for both electrodes of accumulation potential.

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