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    SUPPORT MATRIX FOR INTEGRATED SEMICONDUCTOR AND ITS MANUFACTURING METHOD
    2.
    发明专利
    SUPPORT MATRIX FOR INTEGRATED SEMICONDUCTOR AND ITS MANUFACTURING METHOD 审中-公开

    公开(公告)号：JP2002083906A

    公开(公告)日：2002-03-22

    申请号：JP2001205045

    申请日：2001-07-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAHLISCH KNUT ,  MIETH HENNING

    IPC: H01L23/32 ,  H01L23/02 ,  H01L23/31 ,  H01L23/495

    Abstract: PROBLEM TO BE SOLVED: To provide a means for reliably blocking a flowing silicon material for isolating a support matrix from a semiconductor from creeping into a bonding region of bond leads. SOLUTION: The support matrix for an integrated semiconductor comprises a frame, a conductor path material, at least one bond lead (1) for connecting the conductor path material to the semiconductor, and a silicon material disposed on the support matrix for isolating the support matrix from the semiconductor. The bond lead has at least one groove (7, 8) between a bonding region (3) and the conductor path structure as a barrier to block the silicon material from flowing to the bonding region (3).

    Method for marking failure part
    3.
    发明专利
    Method for marking failure part 审中-公开
    标记失败部分的方法

    公开(公告)号：JP2003332477A

    公开(公告)日：2003-11-21

    申请号：JP2003137224

    申请日：2003-05-15

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： KAHLISCH KNUT ,  MIETH HENNING ,  UHLMANN RUEDIGER

    IPC: H01L23/00 ,  H01L23/544 ,  H05K1/02 ,  H05K3/00 ,  H05K3/22 ,  H05K3/24

    CPC classification number: H05K1/0269 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2924/0002 ,  H05K3/0052 ,  H05K3/225 ,  H05K3/244 ,  H05K2201/09781 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/161 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a method for marking a failure part on a system carrier for mounting a chip in which good recognition can be ensured through an optical recognition system without requiring an extra cost, a durable marking having a sufficient contrast can be formed and occurrence of stamp effect can be prevented surely. SOLUTION: An nonelusive durable BUM marking of a dye different from the surroundings is employed for marking a failure part. BUM marking can also be effected by removing a substance from the surface of the system carrier or by vapor deposition. Instantaneous heating or chemical marking can also be employed. In the region of BUN marking, metal deposited in the vicinity of the surface of a substrate or on the substrate can be subjected locally to permanent discoloring. COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：提供一种用于在系统载体上标记用于安装芯片的故障部分的方法，其中可以通过光学识别系统确保良好的识别，而不需要额外的成本，具有足够对比度的耐用标记 可以形成并且可以确实地防止印记效果的发生。

    解决方案：使用不同于周围环境的染料的非侵入性耐用BUM标记来标记故障部分。 也可以通过从系统载体的表面除去物质或通过气相沉积来实现BUM标记。 也可以采用瞬时加热或化学标记。 在BUN标记的区域中，沉积在基板表面附近或基板上的金属可以在本地进行永久变色。 版权所有（C）2004，JPO

    Producing integrated component for large number of different sizes of microchips, involves ejecting carrier strip with protective layer from cavity or cavities by exerting force on protective layer surface facing cavity using ejector(s)
    6.
    发明专利
    Producing integrated component for large number of different sizes of microchips, involves ejecting carrier strip with protective layer from cavity or cavities by exerting force on protective layer surface facing cavity using ejector(s) 未知

    公开(公告)号：DE102005020427A1

    公开(公告)日：2006-11-09

    申请号：DE102005020427

    申请日：2005-04-29

    Applicant: INFINEON TECHNOLOGIES AG ,  FICO MOLDING SYSTEMS B V

    Inventor： KROEHNERT STEFFEN ,  RAU INGOLF ,  KAHLISCH KNUT ,  HUGEN THEO ,  TEUNISSEN MICHEL

    IPC: H01L21/56 ,  B29C39/36

    Abstract: Producing an integrated component comprises providing a carrier strip with arrangement(s) of chips; placing a casting mold over the carrier strip in such a way that arrangement(s) of chips is covered completely by cavity or cavities of the casting mold; forming a protective layer over arrangement?(s) of chips by filling cavity or cavities with a liquefied encapsulating compound; and ejecting the carrier strip with the protective layer from the cavity or cavities by exerting a force onto a surface of the protective layer facing cavity or cavities. Producing an integrated component comprises providing a carrier strip with arrangement(s) of chips; placing a casting mold over the carrier strip in such a way that arrangement(s) of chips is covered completely by cavity (2) or cavities of the casting mold; forming a protective layer over arrangement?(s) of chips by filling cavity or cavities with a liquefied encapsulating compound; and ejecting the carrier strip with the protective layer from the cavity or cavities by exerting a force onto a surface of the protective layer facing cavity or cavities. The liquefied encapsulating compound transforms into a solid state upon cooling. The force is exerted onto linearly extended surface region(s) of the protective layer. An independent claim is also included for casting mold comprising cavity, and displaceably mounted ejector(s). The cavity is arranged in a contact area. The cavity is delimited by side surfaces (21) and a bottom surface (22). The cavity is designed for the complete coverage of an arrangement of microchips provided on a carrier strip. The ejector(s) is used for ejecting a carrier strip provided with a protective layer. The ejector(s) has linearly extended contact area for the force transmission to the surface of the protective layer.

    7.
    发明专利
    未知

    公开(公告)号：DE10158770A1

    公开(公告)日：2003-06-18

    申请号：DE10158770

    申请日：2001-11-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DOBRITZ STEPHAN ,  KAHLISCH KNUT ,  KROEHNERT STEFFEN

    IPC: H01L23/495 ,  H01L23/50

    Abstract: A leadframe of a conductive material includes a central region to accommodate a chip and a plurality of connecting fingers extending at least from one side in the direction of the central region, a contact region being provided adjacent to the central region on at least some of the connecting fingers. The course of the connecting fingers is such that a sectional face in an arbitrary imaginary cross-section at right angles to the main face of the leadframe has leadframe material. In such a case, it is attempted to keep cross-sections in a component without leadframe material as small as possible.

    8.
    发明专利
    未知

    公开(公告)号：DE10133361A1

    公开(公告)日：2003-01-30

    申请号：DE10133361

    申请日：2001-07-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAHLISCH KNUT ,  MIETH HENNING ,  BISCHOF ANDREAS

    IPC: H01L21/58 ,  H01L23/16 ,  H01L23/31

    Abstract: The inventive method is based on the idea of releasing a mechanical connection between the semiconductor chip and the supporting substrate during the manufacturing of the packing. The mechanical connection required for producing the electrical contacts between the semiconductor chip and the supporting substrate ensues only temporarily. As a result, a critical interface in the packing is removed thereby resulting in distinctly reducing the thermomechanical stresses.

    9.
    发明专利
    未知

    公开(公告)号：DE10030697C2

    公开(公告)日：2002-06-27

    申请号：DE10030697

    申请日：2000-06-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAHLISCH KNUT ,  MIETH HENNING

    IPC: H01L21/58 ,  H01L21/60 ,  H05K3/32

    Abstract: To compensate for mechanical stresses in the substrate (1) a layer of adhesive (2) is applied to it on which is placed a compensating layer (3) in the form of a tape. Then liquid adhesive (4) is applied on top of the tape and the chip (10) placed in position. An alternative method is to use a frame (5) in place of the tape to ensure that the base of the chip is parallel with the substrate surface.

    Support matrix for integrated semiconductors, has frame, conductor track structures, and flowable silicon structures
    10.
    发明专利
    Support matrix for integrated semiconductors, has frame, conductor track structures, and flowable silicon structures 未知

    公开(公告)号：DE10034018A1

    公开(公告)日：2002-01-24

    申请号：DE10034018

    申请日：2000-07-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAHLISCH KNUT ,  MIETH HENNING

    IPC: H01L23/32 ,  H01L23/02 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L21/60 ,  H01L21/58

    Abstract: A support matrix comprises a frame; conductor track structures running on the frame, and having bonding lead(s) for connecting the conductor track structures to an integrated semiconductor; and flowable silicon structures disposed in a region of the bonding lead(s) and serving to space apart the support matrix and the integrated semiconductor. A support matrix comprises a frame; conductor track structures running on the frame, and having bonding lead(s) for connecting the conductor track structures to an integrated semiconductor; and flowable silicon structures disposed in a region of the bonding lead(s) and serving to space apart the support matrix and the integrated semiconductor. The bonding lead has a bonding region, and groove(s) formed between the bonding region and the conductor track structures. The groove (7, 8) functions as a barrier for preventing a flow of the flowable silicon structures onto the bonding region. An Independent claim is also included for a method of producing the support matrix, comprising forming groove(s) between the bonding region of the bonding lead and the conductor track structures; and forming the flowable silicon structures on the frame (12) serving to space apart the support matrix and the semiconductor.

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