公开(公告)号：WO2004027519A3

公开(公告)日：2004-09-23

申请号：PCT/EP0309879

申请日：2003-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： COMMONS MARTIN ,  KLEE VEIT ,  MONO TOBIAS ,  WENSLEY PAUL

IPC: G03F1/00 ,  G03F1/36 ,  G03F1/14

CPC classification number: G03F1/36

Abstract: Disclosed is an optical lithographic mask having one or more dummy patterns, each said dummy pattern having a masked area of said optical lithographic mask seperated from one or more feature masked areas on said optical lithographic mask by an unmasked region of width d, wherein said width d is selected to substantially minimize an average deviation between the dimensions of said feature masked areas and corresponding features etched out upon a semiconductor surface utilizing said optical lithographic mask.

Abstract translation: 公开了一种具有一个或多个虚设图案的光刻掩模，每个所述虚设图案具有所述光刻掩模的掩模区域，所述掩模区域与所述光刻掩模上的一个或多个特征掩模区域隔开宽度为d的未掩模区域， 选择d以基本上最小化所述特征掩模区域的尺寸与利用所述光刻掩模在半导体表面上蚀刻出的对应特征之间的平均偏差。

公开(公告)号：WO03017356A3

公开(公告)日：2003-08-28

申请号：PCT/EP0209009

申请日：2002-08-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WENSLEY PAUL ,  COMMONS MARTIN ,  MONO TOBIAS ,  KLEE VEIT

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8242

CPC classification number: H01L27/10864 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/10861

Abstract: A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.

Abstract translation: 一种为半导体晶片（100）提供浅沟槽（143）隔离的方法。 在第一半导体材料（112）和焊盘氮化物（114）内形成沟槽（113），在沟槽（113）之间的区域中留下第一半导体材料（112）和焊盘氮化物（114）的一部分。 在沟槽（113）上沉积第二半导体材料（116）以将沟槽（113）填充到第一半导体材料（112）顶表面下方的高度。 第一绝缘体（130）选择性地形成在第二半导体材料（116）上方。 焊盘氮化物（114）和沟槽（113）之间的第一半导体材料（112）的一部分被去除以隔离晶片（100）的元件区并且形成具有低电阻的带（142）。

公开(公告)号：WO2007068714A2

公开(公告)日：2007-06-21

申请号：PCT/EP2006069648

申请日：2006-12-13

Applicant: INFINEON TECHNOLOGIES AG ,  KLEE VEIT ,  KNOEFLER ROMAN ,  SCHROEDER PAUL UWE

Inventor： KLEE VEIT ,  KNOEFLER ROMAN ,  SCHROEDER PAUL UWE

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/60 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

Abstract: To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.

Abstract translation: 为了形成半导体器件，在导电区域上方形成绝缘层，并且在绝缘层上方形成图案转印层。 图案转印层被图案化为将形成在绝缘层中的凹陷的布局的相反色调，使得图案转印层保留在将要形成凹陷的区域上方。 掩模材料形成在绝缘层上并与图案转印层对齐。 使用掩模材料作为掩模，去除图案转印层的剩余部分并在绝缘层中蚀刻凹槽。

公开(公告)号：DE112005003840B4

公开(公告)日：2011-07-14

申请号：DE112005003840

申请日：2005-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIM SUNOO ,  KLEE VEIT

IPC: H01L21/336 ,  H01L21/283 ,  H01L21/8234

Abstract: Verfahren zum Ausbilden eines Halbleiterbauelements, wobei das Verfahren folgendes umfaßt: Ausbilden einer Siliziumelektrode (74, 78); Ausbilden einer Seitenwand-Abstandshalterstruktur (50) neben Seitenwänden der Siliziumelektrode (74, 78); Entfernen eines oberen Abschnitts (78) der Siliziumelektrode (74, 78) und Silizidieren eines restlichen Abschnitts (74) der Siliziumelektrode (74, 78); weiterhin umfassend das Reduzieren einer Höhe der Abstandshalterstruktur (50), dadurch gekennzeichnet, dass das Reduzieren der Höhe vor dem Silizidieren durchgeführt wird, und dass das Silizidieren ein vollständiges Silizidieren des restlichen Abschnitts (74) der Siliziumelektrode (74, 78) ist.

公开(公告)号：DE112006003206B4

公开(公告)日：2015-08-06

申请号：DE112006003206

申请日：2006-12-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLEE VEIT ,  KNOEFLER ROMAN ,  SCHROEDER UWE PAUL

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: Verfahren zum Ausbilden einer Halbleiteranordnung mit den Schritten: Ausbilden einer Isolierschicht (16) über einem leitenden Gebiet; Ausbilden einer Siliziumschicht (40) über der Isolierschicht; Ausbilden einer Strukturübertragungsschicht (42) über der Siliziumschicht (40); Entfernen von Teilbereichen der Strukturübertragungsschicht (42) zum Freilegen von Teilbereichen der Siliziumschicht (40), wobei die verbleibenden Teilbereiche der Strukturübertragungsschicht (42) über Teilbereichen der Isolierschicht (16) liegen, in welchen Kontaktlöcher ausgebildet werden; Ändern der freiliegenden Teilbereiche (52) der Siliziumschicht (40), so dass die freiliegenden Teilbereiche (52) der Siliziumschicht (40) von nicht freiliegenden Teilbereichen der Maskierungsschicht (40) verschieden sind; Entfernen der verbleibenden Teilbereiche der Strukturübertragungsschicht (42); Entfernen von Teilbereichen der Siliziumschicht (40), die unter der Strukturübertragungsschicht (42) lagen und während des Veränderungsschrittes nicht verändert wurden, durch ein HF-Ätzen, wobei Teilbereiche der Isolierschicht (16) freigelegt sind, nachdem die nicht reagierten Teilbereiche der Siliziumschicht (40) entfernt worden sind; und Ätzen der freiliegenden Teilbereiche der Isolierschicht (16).

公开(公告)号：DE19927287C2

公开(公告)日：2001-08-23

申请号：DE19927287

申请日：1999-06-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMPEL GEORG ,  HAMMER MARKUS ,  KLEE VEIT ,  JACOB MICHAEL

IPC: H01L21/336 ,  H01L21/8247

公开(公告)号：DE112005002630B4

公开(公告)日：2010-02-25

申请号：DE112005002630

申请日：2005-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIM SUNOO ,  KLEE VEIT

IPC: H01L21/336 ,  H01L21/283 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are silicided at the same time to form a fully silicided (FUSI) gate electrode and silicided source and drain regions.

公开(公告)号：DE112006003206T5

公开(公告)日：2008-10-16

申请号：DE112006003206

申请日：2006-12-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLEE VEIT ,  KNOEFLER ROMAN ,  SCHROEDER UWE PAUL

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/60 ,  H01L21/768

Abstract: To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.

公开(公告)号：DE112005002630T5

公开(公告)日：2007-10-04

申请号：DE112005002630

申请日：2005-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIM SUNOO ,  KLEE VEIT

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/78

Abstract: A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are silicided at the same time to form a fully silicided (FUSI) gate electrode and silicided source and drain regions.