公开(公告)号：WO2004053982A3

公开(公告)日：2004-10-14

申请号：PCT/EP0314172

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM ,  BOLLU MICHAEL ,  KOHLHASE ARMIN ,  LUDWIG CHRISTOPH ,  PALM HERBERT ,  WILLER JOSEF

Inventor： BOLLU MICHAEL ,  KOHLHASE ARMIN ,  LUDWIG CHRISTOPH ,  PALM HERBERT ,  WILLER JOSEF

IPC: H01L21/8246 ,  H01L27/115 ,  G11C1/00

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors (T) in each case run transversely with respect to the relevant word line (2), the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections (21) are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

Abstract translation: 在具有NROM单元的半导体存储器的情况下，各存储晶体管（T）的沟道区域相对于相关字线（2）横向延伸，位线布置在字线的顶侧 并以一种与后者电绝缘的方式，并且存在导电交叉连接件（21），它们以字线间隔布置并以与后者之间的电绝缘方式连接到位线 每个案例在下一个序列中。

公开(公告)号：DE10258194B4

公开(公告)日：2005-11-03

申请号：DE10258194

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： BOLLU MICHAEL ,  PALM HERBERT ,  WILLER JOSEF ,  LUDWIG CHRISTOPH ,  KOHLHASE ARMIN

IPC: H01L21/8246 ,  H01L27/115 ,  H01L21/8247

Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

公开(公告)号：AU2003294845A8

公开(公告)日：2004-06-30

申请号：AU2003294845

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： PALM HERBERT ,  WILLER JOSEF ,  BOLLU MICHAEL ,  KOHLHASE ARMIN ,  LUDWIG CHRISTOPH

IPC: H01L21/8246 ,  H01L27/115

Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

公开(公告)号：AT205334T

公开(公告)日：2001-09-15

申请号：AT93912620

申请日：1993-06-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AUER STEFAN ,  KOHLHASE ARMIN ,  MELZNER HANNO

IPC: H01L21/8242 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/108

Abstract: PCT No. PCT/DE93/00553 Sec. 371 Date May 10, 1995 Sec. 102(e) Date May 10, 1995 PCT Filed Jun. 24, 1993 PCT Pub. No. WO94/00876 PCT Pub. Date Jan. 6, 1994For the global planarization of a semiconductor circuit or a micromechanical component with a step between a higher-lying region and a lower-lying region, the regions being large in area, it is envisaged to deposit a first layer (50), remove it again in the higher-lying region apart from a rib (50), deposit a second layer (51) and then, in a CMP step, planarize the entire arrangement.

公开(公告)号：AT205333T

公开(公告)日：2001-09-15

申请号：AT93912617

申请日：1993-06-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AUER STEFAN ,  KOHLHASE ARMIN ,  MELZNER HANNO

IPC: H01L27/04 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: According to the invention, in the production of a semiconductor storage device with stacked capacitor above bit line storage cells, use is made of a chemical mechanical polishing (CMP) process in which at least the transistor-capacitor contact pillars (9) are produced using one CMP step and there is an overall planarised surface before the bit line (10) is produced. Further CMP steps are applied preferably in the production of the transistor-bit line contact pillar (8) of a bit line (10) embedded in a groove and the lower capacitor plate (11) and for the overall planarisation of the cell field and periphery before the circuit is wired.

公开(公告)号：DE10328577A1

公开(公告)日：2004-03-11

申请号：DE10328577

申请日：2003-06-25

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： HOFMANN FRANZ ,  WILLER JOSEF ,  LUDWIG CHRISTOPH ,  KOHLHASE ARMIN

IPC: H01L21/336 ,  H01L21/8239 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115

Abstract: Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 10 17 cm -3 .

公开(公告)号：DE102005041452A1

公开(公告)日：2007-03-15

申请号：DE102005041452

申请日：2005-08-31

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： ROEPER HEIKO ,  HANKOFER JOHANNES ,  HEDLER HARRY ,  KOHLHASE ARMIN

IPC: H01L25/04

Abstract: Three-dimensional integrated electronic component comprises at least one chip and at least one active and/or passive component on an integrated active substrate comprising a partly divided chip or wafer group, second level mounted assembly circuit on a film on organic and/or inorganic bases with embedded and/or printed circuits forming Plane 1 having redistributed lines or layers and/or conductive traces and wiring (8,11) surfaces (7). The plane is connected to further chips and components and to Plane 2 or additional planes. An independent claim is also included for a production process for the above.

公开(公告)号：AU2003294845A1

公开(公告)日：2004-06-30

申请号：AU2003294845

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  WILLER JOSEF ,  BOLLU MICHAEL ,  KOHLHASE ARMIN ,  LUDWIG CHRISTOPH

IPC: H01L21/8246 ,  H01L27/115

Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

公开(公告)号：DE59310206D1

公开(公告)日：2001-10-11

申请号：DE59310206

申请日：1993-06-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AUER STEFAN ,  KOHLHASE ARMIN ,  MELZNER HANNO

IPC: H01L27/04 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: According to the invention, in the production of a semiconductor storage device with stacked capacitor above bit line storage cells, use is made of a chemical mechanical polishing (CMP) process in which at least the transistor-capacitor contact pillars (9) are produced using one CMP step and there is an overall planarised surface before the bit line (10) is produced. Further CMP steps are applied preferably in the production of the transistor-bit line contact pillar (8) of a bit line (10) embedded in a groove and the lower capacitor plate (11) and for the overall planarisation of the cell field and periphery before the circuit is wired.

公开(公告)号：HK1004999A1

公开(公告)日：1998-12-18

申请号：HK98104230

申请日：1998-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MELZNER HANNO ,  KOHLHASE ARMIN

IPC: G11C11/22 ,  G11C11/24 ,  G11C23/00 ,  G11C

Abstract: The memory with a number of memory cells, such as a read-only (ROM) or dynamic random access (DRAM) memory and the like, is a miniaturised mechanical component. An initial insulation layer (2) is applied over the whole of the main surface of a carrier (1), to be covered over the whole surface by an electrically conductive membrane layer (3). The membrane layer (3) is structured to give the initial conductor paths (4) at the expanded sections (5) of the memory cells. The first insulation layer (2) is given an isotropic etching using the structured membrane layer (3) as the etching mask, until a sharp point (10) remains in the centre directly below the expansion (5). All the remaining material of the insulation layer (2) is removed at the under side of the expansion (5) to form the membrane (5). The membrane can be an oxidation of silicon for the required compressive stress.