公开(公告)号：WO02069284A8

公开(公告)日：2002-11-14

申请号：PCT/EP0201013

申请日：2002-01-31

Applicant: INFINEON TECHNOLOGIES AG ,  PALM HERBERT ,  WOHLRAB ERDMUTE ,  TADDIKEN HANS

Inventor： PALM HERBERT ,  WOHLRAB ERDMUTE ,  TADDIKEN HANS

IPC: G04F10/10 ,  G04F1/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/511 ,  G04F1/005 ,  G04F10/10 ,  H01L29/42324 ,  H01L29/7881 ,  H01L29/792

Abstract: The invention relates to a time-detection device using a floating-gate-cell, wherein an ON-layer structure or a ONO-layer structure is provided between the floating-gate and the control-gate. A charge injection device is supplied in order to insert the floating-gate-electrode into the nitride layer of the ON-structure or the ONO-layer structure, wherein a voltage or a voltage pulse is applied to the control-gate-electrode, the centre of gravity of the charges injected into the nitride layer being located on the defining surface. Said time-detection device also comprises a device for detecting time elapsed since injection of the charges, based on changes in the transmission behaviour of the channel area, which are effected by displacement of the centre of gravity of the charges in the nitride layer away from the defining surface.

Abstract translation: 甲时间检测装置使用在其上设置的导通层结构或浮置栅极和控制栅极之间的ONO层结构的浮动栅极单元。 电荷注入装置被提供到电荷注入到浮置栅电极并进入ON-结构或通过施加电压或电压脉冲的ONO层结构的氮化物层被施加到控制栅电极，在重力的其中一个中心 在位于所述层序列的氧化物层和氮化物层之间的界面处的氮化物层中的注入的电荷。 时间检测装置还包括用于检测由于电荷经过基于在所引起的移位远离在从接口的氮化物层的电荷的重心的沟道区域的传输行为的变化时的喷射的装置。

公开(公告)号：WO0215276A3

公开(公告)日：2002-06-06

申请号：PCT/DE0102997

申请日：2001-08-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  WILLER JOSEF ,  GRATZ ACHIM ,  KRIZ JAKOB ,  ROEHRICH MAYK

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

Abstract: Each memory cell is a memory transistor which is provided with a gate electrode (2) on the upper surface of a semiconductor body. Said gate electrode is disposed in a trench between a source area (3) and a drain area (4) which are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by dielectric material. A series of oxide nitride-oxide layers (5, 6, 7) is disposed between the source area and the drain area and between the drain area and the gate electrode in order to capture charge carriers on the source and drain.

Abstract translation: 每个存储器单元是设置在半导体主体的顶表面上的存储器晶体管，其中栅极电极（2）设置在形成在半导体材料中的源极区（3）和漏极区（4）之间的沟槽中 形成。 栅电极通过介电材料与半导体材料分离。 至少在源区和栅电极之间以及在漏区和栅电极之间存在氧化物 - 氮化物 - 氧化物层序列（5,6,7），其适于在源极和漏极处捕获电荷载流子 被提供。

公开(公告)号：WO0117025A2

公开(公告)日：2001-03-08

申请号：PCT/DE0003002

申请日：2000-09-01

Applicant: INFINEON TECHNOLOGIES AG ,  BRUECKLMEIER ERIC ROGER ,  PALM HERBERT ,  KUX ANDREAS

Inventor： BRUECKLMEIER ERIC-ROGER ,  PALM HERBERT ,  KUX ANDREAS

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/00

CPC classification number: H01L29/7883 ,  H01L29/42328

Abstract: A floating gate cell is used as a clock whereby the charging process is delayed by the application of a sufficiently low charging voltage until a predetermined threshold voltage is reached. A particularly thin tunnel oxide layer can be provided in order to bring about a gradual discharge of a charged cell. Preferably, the floating gate electrode (5)is connected to the control gate electrode (16) of a second cell, which then delays the charging of the floating gate electrode (15) of the second cell.

Abstract translation: 通过在充电过程的时间尺度被延迟，直到通过施加足够低的充电电压的预定阈值电压被使用的浮动栅极单元。 特别薄的隧道可旨在实现加载细胞的逐渐放电。 优选地，浮置栅极电极（5）到所述控制栅电极（16）连接到第二小区，其然后相应地降低时，浮置栅电极（15）加载所述第二小区。

公开(公告)号：WO2004053982A3

公开(公告)日：2004-10-14

申请号：PCT/EP0314172

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM ,  BOLLU MICHAEL ,  KOHLHASE ARMIN ,  LUDWIG CHRISTOPH ,  PALM HERBERT ,  WILLER JOSEF

Inventor： BOLLU MICHAEL ,  KOHLHASE ARMIN ,  LUDWIG CHRISTOPH ,  PALM HERBERT ,  WILLER JOSEF

IPC: H01L21/8246 ,  H01L27/115 ,  G11C1/00

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors (T) in each case run transversely with respect to the relevant word line (2), the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections (21) are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

Abstract translation: 在具有NROM单元的半导体存储器的情况下，各存储晶体管（T）的沟道区域相对于相关字线（2）横向延伸，位线布置在字线的顶侧 并以一种与后者电绝缘的方式，并且存在导电交叉连接件（21），它们以字线间隔布置并以与后者之间的电绝缘方式连接到位线 每个案例在下一个序列中。

公开(公告)号：WO03001600A3

公开(公告)日：2003-08-21

申请号：PCT/DE0202141

申请日：2002-06-12

Applicant: INFINEON TECHNOLOGIES AG ,  PALM HERBERT ,  WILLER JOSEF

Inventor： PALM HERBERT ,  WILLER JOSEF

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L29/66833

Abstract: The invention relates to memory transistors with trenched gate electrodes (2) and an ONO memory layer sequence (5, 6, 7), whose source/drain regions (3, 4) are associated with an electroconductive layer (8) or layer sequence that has a strip-shaped structure that corresponds to the bit lines. Said layer especially comprises a metal silicide or a polysilicon layer (14) with a metallic layer (15) applied thereto that reduces the ohmic resistance of the trenched bit lines. The metal silicide is preferably a cobalt silicide, the metallic layer is preferably a tungsten silicide or WN/W.

Abstract translation: 在源极/漏极区域（3,4），其设置在沟槽栅电极（2）和ONO-存储层序列存储器晶体管（5，6，7）一个对应的带状构成的位线导电层（8）或 层序列排列，特别是金属硅化物或多晶硅层（14），其具有所施加的含金属层（15），其降低了掩埋位线的电阻。 金属硅化物优选为硅化钴; 含金属层优选硅化钨或WN / W。

公开(公告)号：DE50202374D1

公开(公告)日：2005-04-07

申请号：DE50202374

申请日：2002-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  WOHLRAB ERDMUTE ,  TADDIKEN HANS

IPC: G04F10/10 ,  G04F1/00 ,  G07F1/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.

公开(公告)号：DE19941684B4

公开(公告)日：2004-08-26

申请号：DE19941684

申请日：1999-09-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUECKLMEIER ERIC-ROGER ,  PALM HERBERT ,  KUX ANDREAS

IPC: H01L29/423 ,  H01L29/788 ,  H03K5/159

公开(公告)号：AU2003294845A1

公开(公告)日：2004-06-30

申请号：AU2003294845

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  WILLER JOSEF ,  BOLLU MICHAEL ,  KOHLHASE ARMIN ,  LUDWIG CHRISTOPH

IPC: H01L21/8246 ,  H01L27/115

Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

公开(公告)号：DE10039441A1

公开(公告)日：2002-02-28

申请号：DE10039441

申请日：2000-08-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLER JOSEF ,  PALM HERBERT

IPC: H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/792 ,  H01L21/8247

Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body with a gate electrode (2) which is arranged in a trench between a source region (3) and a drain region (4), which are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode there is an oxide-nitride-oxide layer sequence (5, 6, 7), which is provided for the purpose of trapping charge carriers at source and drain.

公开(公告)号：DE10258194B4

公开(公告)日：2005-11-03

申请号：DE10258194

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： BOLLU MICHAEL ,  PALM HERBERT ,  WILLER JOSEF ,  LUDWIG CHRISTOPH ,  KOHLHASE ARMIN

IPC: H01L21/8246 ,  H01L27/115 ,  H01L21/8247

Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.