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公开(公告)号：WO03001361A2
公开(公告)日：2003-01-03
申请号：PCT/DE0202088
申请日：2002-06-07
Applicant: INFINEON TECHNOLOGIES AG , HATSCH JOEL , KAMP WINFRIED , KOEPPE SIEGMAR , KUENEMUND RONALD , LACKERSCHMID EVA , SOELDNER HEINZ
Inventor： HATSCH JOEL , KAMP WINFRIED , KOEPPE SIEGMAR , KUENEMUND RONALD , LACKERSCHMID EVA , SOELDNER HEINZ
CPC classification number: G06F7/607
Abstract: A carry-save adder for adding bits of the same weight comprises six inputs (I0, I1, ...,I5) for receiving six bits, which are to be added and are each of the same weight w. The adder has one output (S) for a sum bit of weight w and two outputs (C0, C1) for two carry bits of the weights 2w and 4w.
Abstract translation: 用于求和等值位的进位保存加法器包括六个输入（I0，I1，...，I5），用于接受要相加的六个相等重要性w的位。 加法器对于权重w的总和位和对于权重2w和4w的两个进位位的两个输出（C0，C1）具有输出（S）。
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公开(公告)号：WO02071203A3
公开(公告)日：2003-04-03
申请号：PCT/DE0200656
申请日：2002-02-22
Applicant: INFINEON TECHNOLOGIES AG , HATSCH JOEL , KOEPPE SIEGMAR , LACKERSCHMID EVA , KAMP WINFRIED , KUENEMUND RONALD , SOELDNER HEINZ
Inventor： HATSCH JOEL , KOEPPE SIEGMAR , LACKERSCHMID EVA , KAMP WINFRIED , KUENEMUND RONALD , SOELDNER HEINZ
CPC classification number: G06F7/509 , G06F7/5016 , G06F7/607 , G06F2207/3872
Abstract: A carry-save adder for adding up bits having the same significance, comprising seven inputs (i0, i1, ..., i6) receiving seven bits having respectively the same significance w for the addition thereof. w. The adder has an output (s) for a sum bit of significance w, in addition to two outputs (c1, c2) for two transfer bits of significance 2w and 4w.
Abstract translation: 为总结的意义相同比特的进位加法器保存有七个输入（I0，I1，...，I6）以接受七位即可概括每个都具有同样的意义W上。 加法器具有用于权重的总和位W和两个输出端（C1，C2），用于化合价的2个位位和2瓦特4瓦特输出（一个或多个）。
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公开(公告)号：DE10139099A1
公开(公告)日：2003-02-27
申请号：DE10139099
申请日：2001-08-09
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HATSCH JOEL , KUENEMUND RONALD , KAMP WINFRIED , LACKERSCHMID EVA , SOELDNER HEINZ , KOEPPE SIEGMAR
Abstract: The carry-ripple adder has 4 inputs (10,11,12,13) for reception of 4 input bits to be summated with the same weighting, 2 further inputs (C10,C11) for opposing entry of carry bits of the weighting, an output (S) for a sum bit of the weighting and 2 outputs (C0,C1) for 2 carry bits of twice and 4 times the weighting. An Independent claim for a carry-accelerated adder is also included.
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公开(公告)号：DE10130484B4
公开(公告)日：2005-08-18
申请号：DE10130484
申请日：2001-06-25
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HATSCH JOEL , KUENEMUND RONALD , KAMP WINFRIED , LACKERSCHMID EVA , SOELDNER HEINZ , KOEPPE SIEGMAR
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公开(公告)号：DE10130483A1
公开(公告)日：2003-03-20
申请号：DE10130483
申请日：2001-06-25
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HATSCH JOEL , KUENEMUND RONALD , KAMP WINFRIED , LACKERSCHMID EVA , SOELDNER HEINZ , KOEPPE SIEGMAR
Abstract: A carry-save adder for adding bits of the same weight comprises six inputs (I0, I1, . . . , I5) for receiving six bits of in each case the same weight w, to be added. The adder has an output (S) for a sum bit of weight w and two outputs (C0, C1) for two carry bits of weights 2w and 4w.
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Patent Agency Ranking
公开(公告)号：DE10117041C1
公开(公告)日：2002-07-25
申请号：DE10117041
申请日：2001-04-05
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HATSCH JOEL , KUENEMUND RONALD , KAMP WINFRIED , LACKERSCHMID EVA , SOELDNER HEINZ , KOEPPE SIEGMAR
Abstract: The adder has 5 inputs (i0,i1,i2,i3,i4) for reception of 5 input bits to be summated with the same value and 2 further inputs (ci0,ci1) for 2 carry-over bits with this value, a first output (s) providing a sum bit equal to the value of the inputs bits and 2 carry-over outputs (c1,c2) providing carry-over bits equal to double this value and 4 times this value. An Independent claim for an adder for summation of bit sets using carry-ripple adders is also included.
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公开(公告)号：DE10139099C2
公开(公告)日：2003-06-18
申请号：DE10139099
申请日：2001-08-09
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HATSCH JOEL , KUENEMUND RONALD , KAMP WINFRIED , LACKERSCHMID EVA , SOELDNER HEINZ , KOEPPE SIEGMAR
Abstract: The carry-ripple adder has 4 inputs (10,11,12,13) for reception of 4 input bits to be summated with the same weighting, 2 further inputs (C10,C11) for opposing entry of carry bits of the weighting, an output (S) for a sum bit of the weighting and 2 outputs (C0,C1) for 2 carry bits of twice and 4 times the weighting. An Independent claim for a carry-accelerated adder is also included.
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公开(公告)号：DE10130484A1
公开(公告)日：2002-09-19
申请号：DE10130484
申请日：2001-06-25
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HATSCH JOEL , KUENEMUND RONALD , KAMP WINFRIED , LACKERSCHMID EVA , SOELDNER HEINZ , KOEPPE SIEGMAR
Abstract: A carry-save adder for adding up bits having the same significance, comprising seven inputs (i0, i1, ..., i6) receiving seven bits having respectively the same significance w for the addition thereof. w. The adder has an output (s) for a sum bit of significance w, in addition to two outputs (c1, c2) for two transfer bits of significance 2w and 4w.
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公开(公告)号：DE19639431C2
公开(公告)日：2002-06-06
申请号：DE19639431
申请日：1996-09-25
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KAMP WINFRIED , KUENEMUND RONALD , LACKERSCHMID EVA , SOELDNER HEINZ
IPC: H01L27/02 , H01L21/82 , H01L21/768
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公开(公告)号：DE10025583A1
公开(公告)日：2001-12-06
申请号：DE10025583
申请日：2000-05-24
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HATSCH JOEL , KAMP WINFRIED , KUENEMUND RONALD , LACKERSCHMID EVA , SOELDNER HEINZ
IPC: G06F17/50 , H01L27/02 , H01L27/118 , H01L21/82
Abstract: The optimisation method has a cell-based network list provided for use in calculating the integrated circuit layout, with extraction of a primary network list from the layout and optimisation of the component dimensions of at least some of the components of the integrated circuit using defined optimisation parameters. A secondary network list is generated using the results of the component optimisation, with subsequent automatic modification of the cell layout. Also included are Independent claims for the following: (a) a device for design of semiconductors; (b) a program object for a cell in a cell library for design of integrated circuits
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