公开(公告)号：DE10207309A1

公开(公告)日：2003-09-11

申请号：DE10207309

申请日：2002-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZUNDEL MARKUS ,  HIRLER FRANZ ,  LANTIER ROBERTA

IPC: H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: An MOS transistor has a trench structure in a semiconductor region. The avalanche breakdown region of the MOS is formed in an end region (30u) or an under region of the trench, especially at the floor (30b). An especially low switching-on resistance of the transistor is thus obtained. An Independent claim is also included for an MOS transistor as above in which there is a maximum dopant concentration (K) between the source (S) and drain (D) regions near the isolation region (GOX).

公开(公告)号：DE10239862A1

公开(公告)日：2004-03-18

申请号：DE10239862

申请日：2002-08-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFIRSCH FRANK ,  HIRLER FRANZ ,  LANTIER ROBERTA

IPC: H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/336

Abstract: A production process for an arrangement of trench transistor cells comprises a doped process layer on a substrate beneath an overlayer with an oppositely doped body region and an underlying drift zone. The body region is implanted to more than 25% of the body depth and the body-drain channel in the drift zone has a not lower doping density than the body region. Independent claims are also included for the following: (a) a trench transistor cell formed as above;and (b) a transistor arrangement as above

公开(公告)号：DE10239862B4

公开(公告)日：2007-03-15

申请号：DE10239862

申请日：2002-08-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFIRSCH FRANK ,  HIRLER FRANZ ,  LANTIER ROBERTA

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78