公开(公告)号：JP2012119711A

公开(公告)日：2012-06-21

申请号：JP2012015456

申请日：2012-01-27

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag

Inventor： HIRLER FRANZ ,  WALTER RIEGER ,  SCHMALZBAUER UWE ,  ZELSACHER RUDOLF ,  ZUNDEL MARKUS

IPC: H01L29/78 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L21/743 ,  H01L23/535 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To resolve a problem that the reliability risk in an actual device may be increased because edge regions of a chip are frequently subjected to a specific burden known and described as a TC stress during a temperature cycle because of different expansion coefficients, and these edge regions are especially likely to be subjected to the TC stress, which may cause various failures in the same region.SOLUTION: An anchoring structure 200 for a metal structure 210 of a semiconductor device includes an anchoring recess structure 220 including at least one overhang-shaped side wall 230. The metal structure 210 is arranged at least partially in the anchoring recess structure 220.

Abstract translation: 要解决的问题：为了解决由于芯片的边缘区域经常遭受已知的并且在温度循环期间由于不同的TC应力而被描述为TC应力的特定负载，因此可能增加实际设备中的可靠性风险的问题 膨胀系数和这些边缘区域特别容易受到TC应力的影响，这可能导致同一区域的各种故障。 解决方案：用于半导体器件的金属结构210的锚固结构200包括具有至少一个悬垂形侧壁230的锚固凹槽结构220.金属结构210至少部分地布置在锚定凹陷结构220中 （C）2012年，JPO＆INPIT

公开(公告)号：JP2009027139A

公开(公告)日：2009-02-05

申请号：JP2008116553

申请日：2008-04-28

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： HIRLER FRANZ ,  WALTER RIEGER ,  SCHMALZBAUER UWE ,  ZELSACHER RUDOLF ,  ZUNDEL MARKUS

IPC: H01L21/3205 ,  H01L23/52 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L21/743 ,  H01L23/535 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an anchoring structure and an intermeshing structure which prevent metal lines from being lifted off from a surface of a chip to come off the chip in a temperature cycling (TC) reliability test for a semiconductor device. SOLUTION: The anchoring structure for a metal structure 210 of the semiconductor device includes an anchoring recess structure 220 having at least one overhanging side wall 230. The metal structure 210 is at least partly arranged within the anchoring recess structure 220. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种锚固结构和啮合结构，其防止在半导体器件的温度循环（TC）可靠性测试中金属线从芯片的表面脱离以脱离芯片。 解决方案：用于半导体器件的金属结构210的锚固结构包括具有至少一个悬垂侧壁230的锚固凹部结构220.金属结构210至少部分地布置在锚定凹部结构220内。

版权所有（C）2009，JPO＆INPIT

公开(公告)号：WO0135466A3

公开(公告)日：2001-11-22

申请号：PCT/EP0011090

申请日：2000-11-09

Applicant: INFINEON TECHNOLOGIES AG ,  HIRLER FRANZ ,  STECHER MATTHIAS ,  NELLE PETER ,  VIETZKE DIRK

Inventor： HIRLER FRANZ ,  STECHER MATTHIAS ,  NELLE PETER ,  VIETZKE DIRK

IPC: H01L21/205 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78 ,  H01L21/20

CPC classification number: H01L29/7813 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/161 ,  H01L29/167

Abstract: In order to prevent misfit caused by the high level of doping, the semiconductor substrate (1) of a field effect transistor, which comprises a body zone (3), is additionally doped with germanium or with carbon that serve to compensate for the misfit.

Abstract translation: 为了避免由于高掺杂失配，在半导体基板（1），其具有主体区（3）的场效应晶体管，另外掺杂有锗或碳作为补偿。

公开(公告)号：WO0052750A3

公开(公告)日：2001-08-09

申请号：PCT/DE0000677

申请日：2000-03-03

Applicant: INFINEON TECHNOLOGIES AG ,  HIRLER FRANZ ,  KANERT WERNER ,  GASSEL HELMUT ,  STRACK HELMUT ,  PAIRITSCH HERBERT

Inventor： HIRLER FRANZ ,  KANERT WERNER ,  GASSEL HELMUT ,  STRACK HELMUT ,  PAIRITSCH HERBERT

IPC: H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L21/225 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802

Abstract: The invention relates to a method for producing a body area for a vertical MOS transistor array in a semiconductor body, wherein the body area has at least one channel region disposed between the source area and the drain area and borders on a gate electrode. A first implantation of doping material is effected in the semiconductor body, wherein the maximum of doping material of the first implantation is placed in the back part of the channel region (11) within the semiconductor body. At least a second implantation of doping material is then effected with a smaller dose than in the first implantation, wherein the maximum of doping material of the second implantation lies within the semiconductor body below the maximum of doping material of the first implantation. Subsequently, the doping material is diffused off.

Abstract translation: 描述一种用于在半导体本体中的垂直MOS晶体管布置，其中所述体区包括至少一个沟道区，设置于栅极电极的源极区域和漏极区域和相邻之间产生的体区的过程。 有掺杂剂至该半导体本体的第一植入物，植入最大与沟道区（11）在半导体本体中的第一植入的复位。 接着进行掺杂材料中的至少一个第二注入具有比第一注入较低的剂量，植入低于最大值的最大注入所述第一注入的半导体主体内的第二植入的位置。 随后，执行掺杂材料的向外扩散。

公开(公告)号：WO2005078802A3

公开(公告)日：2006-02-02

申请号：PCT/DE2005000241

申请日：2005-02-11

Applicant: INFINEON TECHNOLOGIES AG ,  HIRLER FRANZ ,  MAUDER ANTON ,  PFIRSCH FRANK

Inventor： HIRLER FRANZ ,  MAUDER ANTON ,  PFIRSCH FRANK

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L29/808 ,  H01L29/872

CPC classification number: H01L29/0649 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a semiconductor component comprising a drift section (2) that is configured in a semiconductor member (1) and is made of a semiconductor material having a certain type of conductivity. Said drift section (2) is disposed between at least one first and a second electrode (3, 4) and is provided with a trench structure in the form of at least one trench (18). A dielectric material called high-k material is arranged in the trench structure. Said dielectric material has a relative dielectric constant e

Abstract translation: 本发明涉及在一种导电类型的半导体材料的半导体本体（1）形成漂移区（2），其具有的半导体器件。 至少第一和第二电极之间的漂移区（2）（3，4），并具有在至少一个沟槽（18）的形式的严重结构。 在坟墓结构，高k材料设置他20具有相对介电常数ER =，称为介电材料，使得在漂移路径（2）至少一种高k材料区域的区域（5）和半导体材料区域（6 ）所述一种导电类型的布置。

公开(公告)号：WO0213257A3

公开(公告)日：2002-09-19

申请号：PCT/EP0108718

申请日：2001-07-27

Applicant: INFINEON TECHNOLOGIES AG ,  HIRLER FRANZ ,  TIHANYL JENOE ,  WERNER WOLFGANG

Inventor： HIRLER FRANZ ,  TIHANYL JENOE ,  WERNER WOLFGANG

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/739 ,  H01L29/78 ,  H01L29/41

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/7397 ,  H01L29/7828

Abstract: The invention relates to a semiconductor device which can be controlled by means of a field effect. Said device contains a semiconductor body (100) comprising a doped first and second contact area (20, 22, 24, 30) to which connecting electrodes (90, 92) for applying power supply potential are connected. A first control electrode (40, 42, 44; 48, 49) is insulated in relation to the semiconductor body (100; 200) and can be connected to a first control potential. A second control electrode (60, 62, 64; 66, 68; 67, 69; 61, 63) is arranged adjacently in relation to the first control electrode (40, 42, 44; 48, 49). Said second control electrode is arranged in the semiconductor body in an insulated manner and can be connected to a second control potential.

Abstract translation: 本发明通过包括具有掺杂的第一和第二连接区域（20，22，24，30），以连接用于施加电源电势，具有端子电极（90，92）的半导体主体（100）的场效应半导体器件的方法涉及一种可控制的。 第一控制电极（40,42,44,48,49）与半导体本体（100,200）绝缘并且可以连接到第一驱动电位。 邻近于所述第一电极（60，62，64; 66，68; 67，69; 61，63）在半导体本体（100）被布置布置分离的和可连接到第二驱动电势。

公开(公告)号：WO0101484A3

公开(公告)日：2001-08-16

申请号：PCT/DE0001772

申请日：2000-05-30

Applicant: INFINEON TECHNOLOGIES AG ,  LARIK JOOST ,  HIRLER FRANZ ,  KOTEK MANFRED ,  PFIRSCH FRANK

Inventor： LARIK JOOST ,  HIRLER FRANZ ,  KOTEK MANFRED ,  PFIRSCH FRANK

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/36

CPC classification number: H01L29/1095 ,  H01L29/42368 ,  H01L29/7813

Abstract: The invention relates to a trench MOS-transistor, in which the body region (6) is strengthened by an implantation area (7) which faces the drain region (1, 2), in order to increase the avalanche resistance.

Abstract translation: 本发明涉及一种沟槽MOS晶体管，其中体区（6）被增强以通过注入区（7）增加雪崩电阻到漏极区（1,2）。

公开(公告)号：WO0057481A3

公开(公告)日：2001-07-26

申请号：PCT/DE0000621

申请日：2000-03-01

Applicant: INFINEON TECHNOLOGIES AG ,  HIRLER FRANZ ,  WERNER WOLFGANG

Inventor： HIRLER FRANZ ,  WERNER WOLFGANG

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/7813

Abstract: The invention relates to an MOS transistor structure with a trench gate electrode and a reduced specific closing resistor. The integral of the doping concentration of the body region in the lateral direction between two adjacent drift regions is greater than or equal to the integral of the doping concentration in a drift region in the same lateral direction. The invention also relates to methods for producing an MOS transistor structure. Body regions and drift regions are produced by means of epitaxic growth and implantation, repeated epitaxic growth or by filling trenches with doped conduction material.

Abstract translation: 描述了一种具有沟槽栅电极和导通电阻降低的比，从而所述体区的掺杂浓度的在横向方向上的两个相邻的漂移区域之间的积分大于或等于在所述漂移区的掺杂浓度的积分在相同的横向方向上的MOS晶体管结构 ， 此外，方法公开了用于制造MOS晶体管结构，所述体区和漂移区通过外延生长和离子注入，外延生长或通过用掺杂导体材料反复填充沟槽创建。

公开(公告)号：DE112013005770B4

公开(公告)日：2022-12-01

申请号：DE112013005770

申请日：2013-12-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MEISER ANDREAS ,  WEIS ROLF ,  HIRLER FRANZ ,  VIELEMEYER MARTIN ,  ZUNDEL MARKUS ,  IRSIGLER PETER

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/088 ,  H01L29/417

Abstract: Halbleitervorrichtung, die einen ersten Transistor (200, 3002) in einem Halbleiterkörper (100) umfasst, der eine erste Hauptoberfläche (110) hat, wobei der erste Transistor (200, 3002) aufweist:einen benachbart zur ersten Hauptoberfläche (110) angeordneten Sourcebereich (201, 301, 501),einen benachbart zur ersten Hauptoberfläche (110) angeordneten Drainbereich (205, 305, 505),einen Kanalbereich (220, 320, 520),eine Driftzone (260, 360, 560),einen elektrisch mit dem Sourcebereich (201, 301, 501) verbundenen Sourcekontakt (267, 3672, 502),einen elektrisch mit dem Drainbereich (205, 305, 505) verbundenen Drainkontakt (277, 3772, 506),eine Gateelektrode (210, 310, 510) an dem Kanalbereich (220, 320, 520), wobei der Kanalbereich (220, 320, 520) und die Driftzone (260, 360, 560) längs einer ersten Richtung zwischen dem Sourcebereich (201, 301, 501) und dem Drainbereich (205, 305, 505) angeordnet sind, die erste Richtung parallel zu der ersten Hauptoberfläche (110) ist und der Kanalbereich (220, 320, 520) eine Gestalt eines ersten Kammes hat, der sich längs der ersten Richtung erstreckt,wobei der Sourcekontakt (267, 3672, 502) benachbart zu der ersten Hauptoberfläche (110) ist und der Drainkontakt (277, 3772, 506) benachbart zu einer zweiten Hauptoberfläche (120) ist, die entgegengesetzt zu der ersten Hauptoberfläche (110) ist.

公开(公告)号：DE102014111981B4

公开(公告)日：2020-08-13

申请号：DE102014111981

申请日：2014-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAVEN JOHANNES GEORG ,  RÖSNER WOLFGANG ,  DAINESE MATTEO ,  JÄGER CHRISTIAN ,  MAUDER ANTON ,  HIRLER FRANZ ,  STRENZ ROBERT ,  STIFTINGER MARTIN ,  RÖSCH MAXIMILIAN

IPC: H01L29/78 ,  H01L29/739

Abstract: Halbleitervorrichtung, umfassend:einen ersten Lastanschluss (L1), der elektrisch mit Sourcezonen (110) von Transistorzellen (TC) verbunden ist, wobei die Sourcezonen (110) erste pn-Übergänge (pn1) mit Bodyzonen (115) bilden,einen zweiten Lastanschluss (L2), der elektrisch mit einer Drainkonstruktion (120) verbunden ist, die zweite pn-Übergänge (pn2) mit den Bodyzonen (115) bildet, undSteuerstrukturen (400), die direkt an die Bodyzonen (115) angrenzen, wobei die Steuerstrukturen (400) eine Steuerelektrode (420) und Ladungsspeicherstrukturen (410) umfassen, die Steuerelektrode (420) gestaltet ist, um einen Laststrom durch die Bodyzonen (115) zu steuern, die Ladungsspeicherstrukturen (410) die Steuerelektrode (420) von den Bodyzonen (115) isolieren und eine Steuerladung (419) enthalten, die ausgeführt ist, um bei Abwesenheit einer Potentialdifferenz zwischen der Steuerelektrode (420) und dem ersten Lastanschluss (L1) Inversionskanäle in den Bodyzonen (115) zu induzieren, wobeidie Bodyzonen (115) in Halbleitermesas (160) gebildet sind, die von Teilen eines Halbleiterkörpers (100) gebildet und voneinander durch die Steuerstrukturen (400) getrennt sind.