公开(公告)号：WO02063463A3

公开(公告)日：2003-02-06

申请号：PCT/DE0200256

申请日：2002-01-25

Applicant: INFINEON TECHNOLOGIES AG ,  BRUECKLMAYR FRANZ-JOSEF ,  FRIEDINGER HANS ,  SEDLAK HOLGER ,  MAY CHRISTIAN

Inventor： BRUECKLMAYR FRANZ-JOSEF ,  FRIEDINGER HANS ,  SEDLAK HOLGER ,  MAY CHRISTIAN

IPC: G06F12/14 ,  G06F21/24

CPC classification number: G06F12/1483 ,  G06F12/1441

Abstract: The invention relates to a microprocessor circuit for organising access to data or programmes that have been stored in a memory. Said circuit comprises at least one microprocessor, a memory for an operating system and at least one memory for free programming using individual external programmes. The memory used for free programming has several memory areas containing corresponding address spaces, a qualifier being assigned to each address space. The microprocessor circuit also has means, which prior to the respective addressing of a memory area, load each qualifier assigned to a respective memory area into a first auxiliary register and load the qualifier of the addressed memory area into a second auxiliary register and which then compare the first and second auxiliary registers. At least one bit sequence containing access authorisations is also assigned to each address space of a memory area, which allows code commands and sensitive data to be protected from write access emanating from external programmes.

Abstract translation: 本发明提出一种具有至少一个微处理器，用于操作系统的存储器和之前使用单独的外部程序对自由编程的至少一个存储器，其中所述存储器中用于自由编程多个与各存储区组织到存储器存储的数据或程序的访问的微处理器电路 提供的地址空间，其中每一个地址空间被分配的标识符。 微处理器电路还包括用于加载存储器区域的寻址之前在每种情况下分别分配的存储区域的标志为第一辅助寄存器和被寻址的存储器区域的识别符加载到第二辅助寄存器，并且使第一和第二辅助寄存器的比较装置。 它进一步提供分配含有的存储区域，其中代码的命令和敏感的数据从写访问可被保护免受其他外部程序的每个地址空间中的至少一个的访问权限比特序列。

公开(公告)号：WO2004068345A3

公开(公告)日：2007-11-29

申请号：PCT/DE2004000127

申请日：2004-01-28

Applicant: INFINEON TECHNOLOGIES AG ,  MAY CHRISTIAN ,  NOLLES JUERGEN ,  SEDLAK HOLGER

Inventor： MAY CHRISTIAN ,  NOLLES JUERGEN ,  SEDLAK HOLGER

IPC: G06F11/36

CPC classification number: G06F11/3648

Abstract: The invention relates to a method for controlling the interrupt process and/or recording of execution data of a program in a microcontroller (1), whereby a debugging unit (3) is informed by way of a selection attribute associated with a defined program instruction whether a program may be interrupted and/or the pertaining execution data may be recorded while a program instruction is being executed. The invention also relates to a microcontroller (1) which, in addition to the switching circuits and data memories of a microcontroller (2) to be emulated, comprises an arrangement for controlling the interrupt process and/or recording of execution data of a program. The arrangement is characterized in that it comprises a debugging unit (3) and a control logic (5). Said control logic (5) uses a defined selection attribute associated with defined program instructions for deciding whether, in place of a program instruction in a program, the program flow is interrupted and/or the execution data are recorded.

Abstract translation: 本发明涉及一种方法，用于控制中断和/或程序的示例性数据的记录中的微控制器（1），由一个特定的程序指令相关联的选择正在通信属性的调试单元（3）是否在当前执行的程序指令的程序 可能被中断和/或相关联的设计数据被记录。 此外，本发明涉及一种微控制器（1）中，除了上述的电路和数据存储仿真Mikroconrollers（2）具有用于控制中断和/或程序的示例性数据的记录的装置，所述装置包括一个调试单元（3 ）和控制逻辑（5），并且所述控制逻辑（5）的基础上的特定节目的命令相关联的选择属性控制程序是否是在程序中的程序指令的位置被中断和/或性能的数据被记录。

公开(公告)号：WO02099809A2

公开(公告)日：2002-12-12

申请号：PCT/EP0206145

申请日：2002-06-04

Applicant: INFINEON TECHNOLOGIES AG ,  DIRSCHERL GERD ,  HARTLIEB HEIMO ,  MAY CHRISTIAN ,  SEDLAK HOLGER

Inventor： DIRSCHERL GERD ,  HARTLIEB HEIMO ,  MAY CHRISTIAN ,  SEDLAK HOLGER

IPC: G11C8/20

CPC classification number: G11C8/20

Abstract: The invention relates to a method for controlling the mapping of a logical address of a logical address space to a physical address of a physical address space (20). Said method involves the following steps: a first physical address and a corresponding memory cell, which are associated by the mapping (30) of a logical address, are determined; the memory cell is checked for serviceability; and the mapping (30) is modified if the check reveals that the memory cell is not serviceable, in such a way that the logical address is mapped to a second physical address in the physical address space (20). In this way, access to a physical memory is carried out by means of logical addresses which are mapped to the physical addresses of the physical memory, i.e. virtual memory addressing is used in order to mask out non-serviceable memory cells in a simple and effective manner.

Abstract translation: 为一个逻辑地址空间的逻辑地址的图像的用于控制到物理地址空间（20）的物理的本发明的方法包括：确定经由所述映射与逻辑地址相关联的第一物理地址和相关联的存储单元（30），检查 存储器单元自己的能力发挥功能并改变所述映射（30），如果检查的步骤示出了存储单元是无功能的，因此，逻辑地址被映射到物理地址空间（20）的第二物理地址。 以这种方式，通过由一个映射映射到物理存储器，即物理地址的逻辑地址的装置进行访问的物理存储器 虚拟存储器寻址，用于以简单和有效的方式筛选出的非功能存储单元。

公开(公告)号：WO02099645A2

公开(公告)日：2002-12-12

申请号：PCT/EP0205319

申请日：2002-05-14

Applicant: INFINEON TECHNOLOGIES AG ,  GAMMEL BERNDT ,  SEDLAK HOLGER ,  MAY CHRISTIAN ,  LEDWA RALPH

Inventor： GAMMEL BERNDT ,  SEDLAK HOLGER ,  MAY CHRISTIAN ,  LEDWA RALPH

IPC: G06F12/1009 ,  G06F12/00

CPC classification number: G06F12/1009 ,  G06F2212/651 ,  G06F2212/681

Abstract: The invention relates to a method for determining a physical address from a virtual address, whereby a mapping rule is implemented between the virtual address and the physical address in the form of a hierarchical tree structure comprising compressed nodes. According to said method, a compression indicator contained in the mapping rule is first read (1300). Then, a section of the virtual address, which is assigned to the node level under consideration, is read (1310). An entry in the node list of the node currently under consideration is determined (1320) using the compression indicator and the virtual address section. The entry that has been determined is read (1330) and the physical address can then be directly determined, if the node level under consideration was the lowest node level in the hierarchy. If there are additional node levels to be processed, the previous steps are repeated for the determination (1340) of the physical address for compressed nodes of lower hierarchy levels, until the lowest node level in the hierarchy has been reached. For addressing schemes, in which the virtual address space is greater than the physical address space, storage space can be saved by the compression of the node lists, which in their uncompressed form contain a number of zero entries, thus providing space for other data.

Abstract translation: 在用于从虚拟地址确定物理地址的方法，其中，所述虚拟地址和物理地址之间的映射规则为具有节点压缩时，容纳在所述映射规则压缩指示器被第一读（1300）的分层树结构来实现。 另外，所考虑的节点电平相关联的所述虚拟地址的一部分被读取（1310）。 使用压缩指示符和虚拟地址的一部分，在当前考虑的节点的节点列表中的条目被确定（1320）。 所确定的条目被读取（1330），在此之后，物理地址可以直接确定，如果考虑的节点电平是最低分层节点级别。 如果需要的话，进一步被加工节面都存在时，确定（1340）的物理地址时为较低层次的压缩节点重复先前的步骤直到达到最低层次级的节点。 在寻址方案，其中，所述虚拟地址空间是大于物理地址空间大的可通过压缩解压缩，包括壳体节点列表而获得，多个零个条目，存储空间可以被保存并用于其他的数据可用。

公开(公告)号：WO02057906A3

公开(公告)日：2002-11-07

申请号：PCT/DE0200093

申请日：2002-01-15

Applicant: INFINEON TECHNOLOGIES AG ,  MAY CHRISTIAN ,  SEDLAK HOLGER

Inventor： MAY CHRISTIAN ,  SEDLAK HOLGER

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/305 ,  G06F9/42 ,  G06K19/07

CPC classification number: G06F9/30105 ,  G06F9/30127 ,  G06F9/30134

Abstract: The invention relates to a microprocessor circuit comprising a control unit, a memory for free programming with at least one program comprising functions, a stack for the intermediate storage of data and a register bank comprising at least one register which contains an auxiliary register storing a number of bits. Each bit is associated with one of the registers in the register bank and indicates whether or not each register in the register bank contains information.

Abstract translation: 本发明提出了具有控制单元，用于与具有程序的至少一个功能，用于缓冲存储数据和至少一个具有寄存器组寄存器之前的堆叠，其进一步包含Hilfsre-gister包含在多个自由编程存储器的微处理器电路 位存储，其中，每个-的比特被分配给寄存器组的寄存器中的一个，并且指示所述寄存器组中的相应寄存器中是否包含信息或没有。

公开(公告)号：DE50014462D1

公开(公告)日：2007-08-16

申请号：DE50014462

申请日：2000-05-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MAY CHRISTIAN

IPC: G06F1/00 ,  G06F9/38 ,  G06F21/55 ,  G07F7/10

Abstract: Secure data processing unit has a data and program memory (1), a command controller (2) and a control unit (3) for controlling a multiplicity of the function steps of the command controller. An additional empty function generator (4) is provided that generates random empty functions and thus also causes empty input-output processes. An independent claim is made for a method for securing a data processing unit against electronic eavesdropping in which additional empty transmit and receive processes are initiated.

公开(公告)号：AT294414T

公开(公告)日：2005-05-15

申请号：AT00110838

申请日：2000-05-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MAY CHRISTIAN

IPC: G06F1/00 ,  G06F9/38 ,  G06F21/55 ,  G07F7/10

Abstract: Secure data processing unit has a data and program memory (1), a command controller (2) and a control unit (3) for controlling a multiplicity of the function steps of the command controller. An additional empty function generator (4) is provided that generates random empty functions and thus also causes empty input-output processes. An independent claim is made for a method for securing a data processing unit against electronic eavesdropping in which additional empty transmit and receive processes are initiated.

公开(公告)号：AT269578T

公开(公告)日：2004-07-15

申请号：AT01985373

申请日：2001-12-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUECKLMAYR FRANZ-JOSEF ,  MAY CHRISTIAN ,  POCKRANDT WOLFGANG ,  SEDLAK HOLGER

IPC: G06F12/16 ,  G11C16/10

公开(公告)号：BR9914396A

公开(公告)日：2001-06-26

申请号：BR9914396

申请日：1999-10-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MAY CHRISTIAN ,  FREIWALD JUERGEN ,  BRIXEL OLAF

IPC: G06F9/42 ,  G06F8/41 ,  G06F9/00 ,  G06F9/45 ,  G06F11/00 ,  G06F12/14

Abstract: An efficient method for protecting entry addresses in computer programs allows direct jumps to permissible entry addresses. The permissible entry addresses are identified with a correlation of data which are not provided within the same individual instruction. By organizing the program code, the compiler or linker ensures that only legal entry addresses satisfy this correlation.

公开(公告)号：ES2214062T3

公开(公告)日：2004-09-01

申请号：ES99970480

申请日：1999-10-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MAY CHRISTIAN ,  FREIWALD JURGEN ,  BRIXEL OLAF

IPC: G06F9/42 ,  G06F8/41 ,  G06F9/00 ,  G06F9/45 ,  G06F11/00 ,  G06F12/14

Abstract: An efficient method for protecting entry addresses in computer programs allows direct jumps to permissible entry addresses. The permissible entry addresses are identified with a correlation of data which are not provided within the same individual instruction. By organizing the program code, the compiler or linker ensures that only legal entry addresses satisfy this correlation.